Inventor · disambiguated record
Nikhil Vishwanath Kelkar
Also filed as: KELKAR NIKHIL · KELKAR NIKHIL V · KELKAR NIKHIL VISHWANATH
53 granted patents·7 pending applications·1,503 citations·filing 1997–2017
99Inventor score
Files withNAT SEMICONDUCTOR CORP37Intersil Americas LLC6KELKAR NIKHIL VISHWANATH3HEBERT FRANCOIS2INTERSIL INC2
Top patents by PatentIndex Score
60 records- 0196US7923300B2Stacked power converter structure and methodINTERSIL INC·Filed 2009·Granted Apr 12, 2011·24 cites·6 claims
- 0295US6521970B1Chip scale package with compliant leadsNAT SEMICONDUCTOR CORP·Filed 2000·Granted Feb 18, 2003·97 cites·12 claims
- 0395US6084308AChip-on-chip integrated circuit package and method for making the sameNAT SEMICONDUCTOR CORP·Filed 1998·Granted Jul 4, 2000·244 cites·19 claims
- 0495US6075290ASurface mount die: wafer level chip-scale package and process for making the sameNAT SEMICONDUCTOR CORP·Filed 1998·Granted Jun 13, 2000·250 cites·18 claims
- 0594US6462426B1Barrier pad for wafer level chip scale packagesNAT SEMICONDUCTOR CORP·Filed 2000·Granted Oct 8, 2002·104 cites·21 claims
- 0692US6023094ASemiconductor wafer having a bottom surface protective coatingNAT SEMICONDUCTOR CORP·Filed 1998·Granted Feb 8, 2000·116 cites·6 claims
- 0790US6175162B1Semiconductor wafer having a bottom surface protective coatingNAT SEMICONDUCTOR CORP·Filed 1999·Granted Jan 16, 2001·92 cites·7 claims
- 0889US9607917B2Stacked inductor-electronic package assembly and technique for manufacturing sameMOUSSAOUI ZAKI·Filed 2010·Granted Mar 28, 2017·10 cites·24 claims
- 0989US8324602B2Optical sensors that reduce specular reflectionsWIESE LYNN K·Filed 2009·Granted Dec 4, 2012·23 cites·29 claims
- 1088US6448632B1Metal coated markings on integrated circuit devicesNAT SEMICONDUCTOR CORP·Filed 2000·Granted Sep 10, 2002·49 cites·13 claims
- 1187US8508052B2Stacked power converter structure and methodBELL DAVID B·Filed 2011·Granted Aug 13, 2013·5 cites·10 claims
- 1286US7375431B1Solder bump formation in electronics packagingNAT SEMICONDUCTOR CORP·Filed 2005·Granted May 20, 2008·12 cites·13 claims
- 1385US7135385B1Semiconductor devices having a back surface protective coatingNAT SEMICONDUCTOR CORP·Filed 2004·Granted Nov 14, 2006·43 cites·10 claims
- 1484US7045035B1Post singulation die separation apparatus and method for bulk feeding operationNAT SEMICONDUCTOR CORP·Filed 2005·Granted May 16, 2006·8 cites·15 claims
- 1583US6900532B1Wafer level chip scale packageNAT SEMICONDUCTOR CORP·Filed 2000·Granted May 31, 2005·31 cites·19 claims
- 1681US7420280B1Reduced stress under bump metallization structureNAT SEMICONDUCTOR CORP·Filed 2005·Granted Sep 2, 2008·10 cites·18 claims
- 1781US7241643B1Wafer level chip scale packageNAT SEMICONDUCTOR CORP·Filed 2005·Granted Jul 10, 2007·8 cites·15 claims
- 1880US7095116B1Aluminum-free under bump metallization structureNAT SEMICONDUCTOR CORP·Filed 2003·Granted Aug 22, 2006·42 cites·18 claims
- 1979US7642175B1Semiconductor devices having a back surface protective coatingNAT SEMICONDUCTOR CORP·Filed 2006·Granted Jan 5, 2010·9 cites·6 claims
- 2079US6932136B1Post singulation die separation apparatus and method for bulk feeding operationNAT SEMICONDUCTOR CORP·Filed 2004·Granted Aug 23, 2005·19 cites·20 claims
- 2179US6916688B1Apparatus and method for a wafer level chip scale package heat sinkNAT SEMICONDUCTOR CORP·Filed 2002·Granted Jul 12, 2005·25 cites·13 claims
- 2278US8951847B2Package leadframe for dual side assemblyKELKAR NIKHIL VISHWANATH·Filed 2012·Granted Feb 10, 2015·5 cites·11 claims
- 2377US9012267B2Method of manufacturing a packaged circuit including a lead frame and a laminate substrateIntersil Americas LLC·Filed 2013·Granted Apr 21, 2015·3 cites·4 claims
- 2477USRE38789ESemiconductor wafer having a bottom surface protective coatingNAT SEMICONDUCTOR CORP·Filed 2001·Granted Sep 6, 2005·19 cites·15 claims
- 2575US6803648B1Integrated circuit packages with interconnects on top and bottom surfacesNAT SEMICONDUCTOR CORP·Filed 2003·Granted Oct 12, 2004·22 cites·16 claims
- 2675US6327158B1Metal pads for electrical probe testing on wafer with bump interconnectsNAT SEMICONDUCTOR CORP·Filed 1999·Granted Dec 4, 2001·46 cites·15 claims
- 2774US7230580B1Design of a two interconnect IC chip for a radio frequency identification tag and method for manufacturing sameNAT SEMICONDUCTOR CORP·Filed 2003·Granted Jun 12, 2007·20 cites·15 claims
- 2873US8232541B2Optical sensors that reduce specular reflectionsWIESE LYNN K·Filed 2009·Granted Jul 31, 2012·6 cites·29 claims
- 2972US6822315B2Apparatus and method for scribing semiconductor wafers using vision recognitionNAT SEMICONDUCTOR CORP·Filed 2002·Granted Nov 23, 2004·14 cites·14 claims
- 3071US7674702B1Solder bump formation in electronics packagingNAT SEMICONDUCTOR CORP·Filed 2008·Granted Mar 9, 2010·4 cites·20 claims
- 3171US7510908B1Method to dispense light blocking material for wafer level CSPNAT SEMICONDUCTOR CORP·Filed 2005·Granted Mar 31, 2009·5 cites·13 claims
- 3271US7015064B1Marking wafers using pigmentation in a mounting tapeNAT SEMICONDUCTOR CORP·Filed 2004·Granted Mar 21, 2006·17 cites·7 claims
- 3371US6566762B1Front side coating for bump devicesNAT SEMICONDUCTOR CORP·Filed 2002·Granted May 20, 2003·15 cites·20 claims
- 3471US6249044B1Opaque metallization to cover flip chip die surface for light sensitive semiconductor devicesNAT SEMICONDUCTOR CORP·Filed 1999·Granted Jun 19, 2001·38 cites·14 claims
- 3567US8946875B2Packaged semiconductor devices including pre-molded lead-frame structures, and related methods and systemsIntersil Americas LLC·Filed 2012·Granted Feb 3, 2015·2 cites·16 claims
- 3662US8558396B2Bond pad configurations for semiconductor diesKELKAR NIKHIL VISHWANATH·Filed 2011·Granted Oct 15, 2013·2 cites·19 claims
- 3761US6900110B1Chip scale package with compliant leadsNAT SEMICONDUCTOR CORP·Filed 2002·Granted May 31, 2005·8 cites·7 claims
- 3860US9723766B2Power supply module with electromagnetic-interference (EMI) shielding, cooling, or both shielding and cooling, along two or more sidesYIN JIAN·Filed 2011·Granted Aug 1, 2017·1 cites·45 claims
- 3960US6972244B1Marking semiconductor devices through a mount tapeNAT SEMICONDUCTOR CORP·Filed 2004·Granted Dec 6, 2005·12 cites·5 claims
- 4058US8635762B1Methods for manufacturing a radio frequency identification tag without aligning the chip and antennaKELKAR NIKHIL V·Filed 2006·Granted Jan 28, 2014·3 cites·6 claims
- 4158US6468892B1Front side coating for bump devicesNAT SEMICONDUCTOR CORP·Filed 2000·Granted Oct 22, 2002·7 cites·13 claims
- 4258US6398034B1Universal tape for integrated circuitsNAT SEMICONDUCTOR CORP·Filed 2000·Granted Jun 4, 2002·7 cites·14 claims
- 4354US7714415B2Leadframe structures for semiconductor packagesINTERSIL INC·Filed 2006·Granted May 11, 2010·1 cites·12 claims
- 4453US10582617B2Method of fabricating a circuit moduleIntersil Americas LLC·Filed 2017·Granted Mar 3, 2020·0 cites·15 claims
- 4553US7282375B1Wafer level package design that facilitates trimming and testingNAT SEMICONDUCTOR CORP·Filed 2004·Granted Oct 16, 2007·5 cites·13 claims
- 4653US2014103120A1Methods for manufacturing a radio frequency identification tag without aligning the chip and antennaNAT SEMICONDUCTOR CORP·Filed 2013·Application pending·0 cites
- 4751US9717146B2Circuit module such as a high-density lead frame array (HDA) power module, and method of making sameYIN JIAN·Filed 2012·Granted Jul 25, 2017·0 cites·12 claims
- 4851US9613889B2Packaged circuit with a lead frame and laminate substrateIntersil Americas LLC·Filed 2015·Granted Apr 4, 2017·0 cites·16 claims
- 4950US2017162488A1Packaged circuit with a lead frame and laminate substrateIntersil Americas LLC·Filed 2017·Application pending·0 cites
- 5049US2020266159A9Method of making a stacked inductor-electronic packageIntersil Americas LLC·Filed 2017·Application pending·0 cites
Showing the top 50 of 60 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →