Semiconductor device and method for fabricating the same

Abstract

A semiconductor device includes: a fin-shaped structure on a substrate, in which the fin-shaped structure includes a top portion and a bottom portion; a doped layer around the bottom portion of the fin-shaped structure; a first liner on the doped layer, and a second liner on the top portion and the bottom portion of the fin-shaped structure. Preferably, the first liner and the second liner are made of different material.

What is claimed is: 
     
       1. A method for fabricating semiconductor device, comprising:
 providing a substrate having a first region and a second region defined thereon; 
 forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; 
 forming a first doped layer on the first fin-shaped structure and the second fin-shaped structure and a first liner on the first doped layer; and 
 forming a second doped layer around the bottom portion of the first fin-shaped structure and a second liner on the second doped layer after removing the first doped layer and the first liner on the first region. 
 
     
     
       2. The method of  claim 1 , further comprising:
 forming the first doped layer on the first fin-shaped structure and the second fin-shaped structure; 
 forming the first liner on the first doped layer; 
 removing the first liner and the first doped layer from the first fin-shaped structure; 
 forming the second doped layer on the first fin-shaped structure and the second fin-shaped structure; 
 removing the second doped layer from the second fin-shaped structure; 
 forming the second liner on the first fin-shaped structure and the second fin-shaped structure; 
 forming a dielectric layer on the second liner and around the bottom portions of the first fin-shaped structure and the second fin-shaped structure; and 
 removing the second liner, the second doped layer, the first liner, and the first doped layer from the top portions of the first fin-shaped structure and the second fin-shaped structure. 
 
     
     
       3. The method of  claim 2 , further comprising:
 forming the dielectric layer on the second liner; 
 removing part of the dielectric layer so that the top surface of the dielectric layer is between the top portions and the bottom portions of the first fin-shaped structure and the second fin-shaped structure; and 
 removing the second liner, the second doped layer, the first liner, and the first doped layer to expose the top portions of the first fin-shaped structure and the second fin-shaped structure. 
 
     
     
       4. The method of  claim 2 , further comprising performing an annealing process on the second liner, the second doped layer, the first liner, and the first doped layer around the bottom portions of the first fin-shaped structure and the second fin-shaped structure after removing the second liner, the second doped layer, the first liner, and the first doped layer from the top portions of the first fin-shaped structure and the second fin-shaped structure. 
     
     
       5. The method of  claim 1 , wherein the first region comprises a PMOS region, the first doped layer comprises borosilicate glass (BSG), the second region comprises a NMOS region, and the second doped layer comprises phosphosilicate glass (PSG). 
     
     
       6. The method of  claim 1 , further comprising forming a hard mask on the first fin-shaped structure and the second fin-shaped structure before forming the first doped layer. 
     
     
       7. The method of  claim 1 , further comprising forming a third liner on the top portions and the bottom portions of the first fin-shaped structure and the second fin-shaped structure before forming the first doped layer. 
     
     
       8. The method of  claim 7 , wherein the first liner and the second liner comprise silicon nitride, and the third liner comprises silicon oxide.