Three dimensional memory device containing multilayer wordline barrier films and method of making thereof

Abstract

Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. A barrier layer stack including a crystalline electrically conductive barrier layer and an amorphous barrier layer is formed in the backside recesses prior to formation of a metal fill material layer.

What is claimed is: 
     
       1. A method of forming a three-dimensional memory device, comprising:
 forming an alternating stack of insulating layers and sacrificial material layers over a semiconductor substrate; 
 forming memory stack structures through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; 
 forming backside recesses by removing the sacrificial material layers selective to the insulating layers and the memory stack structures; 
 forming an amorphous barrier layer in the backside recesses; 
 forming a metal fill material layer within remaining volumes of the backside recesses after formation of the amorphous barrier layer; 
 forming a polycrystalline electrically conductive barrier layer in the backside recesses; and 
 annealing the amorphous barrier layer after depositing the metal fill material to convert the amorphous barrier layer to a polycrystalline barrier layer, wherein the metal fill material layer comprises tungsten, the amorphous barrier layer comprises titanium oxide and the polycrystalline electrically conductive barrier layer comprises titanium oxide. 
 
     
     
       2. The method of  claim 1 , wherein:
 the metal fill material layer comprises a word line of the three-dimensional memory device; 
 the polycrystalline electrically conductive barrier layer and the amorphous barrier layer have different material compositions; 
 the amorphous barrier layer includes an amorphous material formed at a step of depositing the metal fill material layer; and 
 the amorphous barrier layer is an electrically conductive amorphous material layer or a non-conductive amorphous material layer. 
 
     
     
       3. The method of  claim 1 , wherein:
 the polycrystalline electrically conductive barrier layer is deposited directly on the amorphous barrier layer; and 
 the metal fill material layer is deposited directly on the polycrystalline electrically conductive barrier layer. 
 
     
     
       4. The method of  claim 1 , further comprising depositing a backside blocking dielectric layer in the backside recesses and directly on sidewalls of the memory stack structures, wherein the amorphous barrier layer is formed over the backside blocking dielectric layer. 
     
     
       5. The method of  claim 1 , wherein:
 the metal fill material layer comprises tungsten; 
 the polycrystalline electrically conductive barrier layer comprises a material selected from TiN, TaN, WN, Ti, and Ta; and 
 the amorphous barrier layer comprises a material selected from TiSiN, TiCN, TiBN, TiAlN, WCB, WBN, TiGeBN, amorphous TiN, Si 3 N 4 , TiO x , and TaO y , wherein x is in a range from 1.7 to 2.3 and y is in a range from 1.8 to 2.8. 
 
     
     
       6. The method of  claim 1 , wherein:
 the three-dimensional memory array comprises a monolithic three-dimensional NAND memory device; 
 the metal fill material layer comprises, or is electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device; 
 the substrate comprises a silicon substrate; 
 the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate; 
 at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings; 
 the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; 
 the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and 
 the array of monolithic three-dimensional NAND strings comprises:
 a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and 
 a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels. 
 
 
     
     
       7. A method of forming a three-dimensional memory device, comprising:
 forming an alternating stack of insulating layers and sacrificial material layers over a semiconductor substrate; 
 forming memory stack structures through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; 
 forming backside recesses by removing the sacrificial material layers selective to the insulating layers and the memory stack structures; 
 forming an alternating barrier stack of titanium nitride layers and boron-containing layers; 
 depositing a metal fill material layer within remaining volumes of the backside recesses after formation of the alternating barrier stack; and 
 annealing the alternating barrier stack to form a TiBN layer having an undulating boron concentration as a function of distance from a most proximal one of the insulating layers. 
 
     
     
       8. The method of  claim 7 , wherein the boron-containing layers are formed by decomposition of a boron-containing precursor on a surface of one of the titanium nitride layers and comprises atomic boron or BN. 
     
     
       9. The method of  claim 7 , wherein each of the boron-containing layers is formed by deposition of a boron layer on an underlying titanium nitride layer and subsequent nitridation of the boron layer, and wherein each of the boron-containing layers has a thickness in a range from 0.01 nm to 0.5 nm. 
     
     
       10. A three-dimensional memory device comprising:
 an alternating stack of insulating layers and electrically conductive layers located over a substrate; and 
 memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel laterally surrounded by the memory film, 
 wherein each of the electrically conductive layers comprises:
 at least a ternary transition metal boronitride barrier layer; and 
 a metal fill material layer spaced from the insulating layers and the memory stack structures by the barrier layer; 
 
 wherein: 
 the metal fill material layer comprises a word line of the three-dimensional memory device; and 
 the at least the ternary transition metal boronitride barrier layer comprises a titanium boronitride layer in which a boron concentration undulates as a function of thickness. 
 
     
     
       11. A method of forming a three-dimensional memory device, comprising: forming an alternating stack of insulating layers and sacrificial material layers over a semiconductor substrate; forming memory stack structures through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; forming backside recesses by removing the sacrificial material layers selective to the insulating layers and the memory stack structures; forming a first amorphous barrier layer in the backside recesses; forming a polycrystalline electrically conductive barrier layer in the backside recesses; forming a second amorphous barrier layer in the backside recesses; and forming a metal fill material layer within remaining volumes of the backside recesses after formation of the second amorphous barrier layer; wherein: the second amorphous barrier layer is deposited directly on the polycrystalline electrically conductive barrier layer; the metal fill material layer comprises tungsten which is deposited employing a fluorine containing precursor gas that etches, partly or completely, the second amorphous barrier layer during deposition of the metal fill material layer; and the polycrystalline electrically conductive barrier layer is deposited directly on the first amorphous barrier layer.