Semiconductor package having routable encapsulated conductive substrate and method

Abstract

A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

What is claimed is: 
     
       1. A semiconductor device structure comprising:
 a routable encapsulated conductive substrate comprising:
 a first conductive structure encapsulated within a first laminated layer, wherein:
 the first conductive structure comprises:
 a first surface finish layer; and 
 first conductive vias coupled to at least a portion of the first surface finish layer; and 
 
 the first laminated layer defines a top substrate surface of the routable encapsulated conductive substrate; 
 the first surface finish layer is exposed by the top substrate surface; 
 
 a second conductive structure electrically coupled to the first conductive vias and encapsulated within a second laminated layer, wherein:
 the second conductive structure comprises:
 a conductive pattern structure; and 
 conductive pads connected to the conductive pattern structure; 
 
 the second laminated layer defines a bottom substrate surface of the routable encapsulated conductive substrate; 
 the second laminated layer covers a portion of the first laminated layer; and 
 lower surfaces of the conductive pads proximate to the bottom substrate surface are devoid of the second laminated layer so that the lower surfaces are adapted for coupling to a next level assembly; 
 
 
 a semiconductor device electrically coupled to the first surface finish layer and 
 a package body covering the semiconductor device, at least portions of the first surface finish layer, and at least portions of the top substrate surface. 
 
     
     
       2. The semiconductor device structure of  claim 1 , wherein:
 the first surface finish layer and the first conductive vias comprise different conductive materials. 
 
     
     
       3. The semiconductor device structure of  claim 2 , wherein:
 the first surface finish layer comprises silver (Ag); and 
 the first conductive vias comprise copper (Cu). 
 
     
     
       4. The semiconductor device structure of  claim 1 , wherein:
 the semiconductor device is attached to the top substrate surface; and 
 the semiconductor device is electrically connected to the first surface finish layer structure with conductive wires. 
 
     
     
       5. The semiconductor device structure of  claim 1 , further comprising:
 first conductive patterns disposed within the first laminated layer, wherein:
 a first part of the first conductive patterns are interposed between the first conductive vias and the first surface finish layer; and 
 a second part of the first conductive patterns are devoid of the first conductive vias and devoid of the first surface finish layer. 
 
 
     
     
       6. The semiconductor device of  claim 1 , wherein:
 a portion of the conductive pattern structure is provided devoid of the conductive pads. 
 
     
     
       7. The semiconductor device of  claim 1 , wherein:
 the first surface finish layer is substantially coplanar with the top substrate surface; 
 surfaces of the conductive pads are recessed within openings in the second laminated layer; and 
 the semiconductor device further comprises a second surface finish layer coupled to the conductive pads. 
 
     
     
       8. The semiconductor device of  claim 1  further comprising a second surface finish layer connected to the conductive pads. 
     
     
       9. The semiconductor device of  claim 8 , wherein:
 the second surface finish layer comprises one or more of nickel/gold (Ni/Au), silver (Ag) or tin (Sn). 
 
     
     
       10. A semiconductor device structure comprising:
 a routable encapsulated conductive substrate comprising:
 a first conductive structure encapsulated within a first laminated layer, wherein:
 the first conductive structure comprises:
 a first surface finish layer; and 
 first conductive vias connected to at least a portion of the first surface finish layer; and 
 
 the first laminated layer defines a top substrate surface of the routable encapsulated conductive substrate; 
 the first surface finish layer is exposed by the top substrate surface; 
 
 a second conductive structure electrically coupled to the first conductive vias and encapsulated within a second laminated layer, wherein:
 the second conductive structure comprises:
 a conductive pattern structure; and 
 conductive pads connected to the conductive pattern structure; 
 
 the second laminated layer defines a bottom substrate surface of the routable encapsulated conductive substrate; 
 the second laminated layer covers a portion of the first laminated layer; 
 lower surfaces of the conductive pads proximate to the bottom substrate surface are devoid of the second laminated layer so that the lower surfaces are adapted for coupling to a next level assembly; and 
 a second surface finish layer is coupled to the lower surfaces of the conductive pads; 
 
 
 a semiconductor device electrically coupled to the first surface finish layer; and 
 a package body covering the semiconductor device, at least portions of the first surface finish layer, and at least portions of the top substrate surface. 
 
     
     
       11. The semiconductor device of  claim 10 , wherein:
 the first surface finish layer and the first conductive vias comprise different conductive materials; 
 surfaces of the conductive pads are recessed within openings in the second laminated layer; and 
 the second surface finish layer is substantially coplanar with an outer surface of the second laminated layer. 
 
     
     
       12. The semiconductor device structure of  claim 10 , wherein:
 the first surface finish layer comprises silver (Ag); and 
 the first conductive vias comprise copper (Cu). 
 
     
     
       13. The semiconductor device structure of  claim 10 , further comprising:
 first conductive patterns disposed within the first laminated layer, wherein:
 a first part of the first conductive patterns are disposed between the first conductive vias and the first surface finish layer; and 
 a second part of the first conductive patterns are devoid of the first conductive vias and devoid of the first surface finish layer. 
 
 
     
     
       14. The semiconductor device of  claim 10 , wherein:
 a portion of the conductive pattern structure is provided devoid of the conductive pads. 
 
     
     
       15. A semiconductor device structure comprising:
 a routable encapsulated conductive substrate comprising:
 a first conductive structure encapsulated within a first laminated layer, wherein:
 the first conductive structure comprises:
 a first surface finish layer; and 
 first conductive vias connected to at least a portion of the first surface finish layer; and 
 
 the first laminated layer defines a top substrate surface of the routable encapsulated conductive substrate; 
 the first surface finish layer is exposed by the top substrate surface; 
 
 a second conductive structure electrically coupled to the first conductive vias and encapsulated within a second laminated layer, wherein:
 the second conductive structure comprises:
 a conductive pattern structure; and 
 conductive pads connected to the conductive pattern structure; 
 
 the second laminated layer defines a bottom substrate surface of the routable encapsulated conductive substrate; 
 the second laminated layer covers a portion of the first laminated layer; 
 lower surfaces of the conductive pads proximate to the bottom substrate surface are devoid of the second laminated layer so that the lower surfaces are adapted for coupling to a next level assembly; and 
 a second surface finish layer is coupled to the lower surfaces of the conductive pads; 
 
 
 a semiconductor device electrically coupled to the first surface finish layer; and 
 a package body covering the semiconductor device, at least portions of the first surface finish layer, and at least portions of the top substrate surface, wherein:
 the first surface finish layer and the first conductive vias comprise different conductive materials. 
 
 
     
     
       16. The semiconductor device structure of  claim 15 , wherein:
 the first surface finish layer comprises silver (Ag); and 
 the first conductive vias comprise copper (Cu). 
 
     
     
       17. The semiconductor device of  claim 15 , wherein:
 surfaces of the conductive pads are recessed within openings in the second laminated layer; 
 the second surface finish layer is substantially coplanar with an outer surface of the second laminated layer. 
 
     
     
       18. The semiconductor device of  claim 15 , further comprising:
 first conductive patterns disposed within the first laminated layer, wherein:
 a first part of the first conductive patterns are disposed between the first conductive vias and the first surface finish layer; 
 a second part of the first conductive patterns are devoid of the first conductive vias and devoid of the first surface finish layer; and 
 at least a portion of the second part is recessed below the top substrate surface. 
 
 
     
     
       19. The semiconductor device of  claim 15 , wherein:
 the first surface finish layer is substantially coplanar with the top substrate surface. 
 
     
     
       20. The semiconductor device structure of  claim 15 , wherein:
 second surface finish layer comprises one or more of nickel/gold (Ni/Au), silver (Ag) or tin (Sn).