Alignment marks in substrate having through-substrate via (TSV)

Abstract

A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.

What is claimed is: 
     
       1. A method comprising:
 forming a first through-substrate via (TSV) and a second TSV in a substrate, wherein the forming of the first TSV and the second TSV comprises a photolithography process that simultaneously defines patterns for the first TSV and the second TSV using a single lithography mask; 
 forming an interconnect structure on a front side of the substrate, wherein the interconnect structure comprises:
 a first alignment mark aligned to the second TSV; and 
 a first conductive feature disposed in a dielectric layer; 
 
 reducing a thickness of a back side of the substrate such that the first TSV and the second TSV protrude beyond the back side of the substrate; and 
 forming a second conductive feature on the back side of the substrate, the second conductive feature being electrically connected to the first conductive feature through the first TSV, the second TSV being isolated from circuitry of the interconnect structure. 
 
     
     
       2. The method of  claim 1 , wherein the second TSV is used as a second alignment mark for positioning the second conductive feature. 
     
     
       3. The method of  claim 1 , wherein the first alignment mark is formed in a first-level metal layer of the interconnect structure. 
     
     
       4. The method of  claim 1 , wherein the first alignment mark is formed in a metal layer of the interconnect structure. 
     
     
       5. The method of  claim 1  further comprising forming an active or a passive device on the front side of the substrate. 
     
     
       6. The method of  claim 1  further comprising after reducing the thickness of the back side of the substrate, forming a passivation layer over the back side of the substrate and protruding portions of the first TSV and the second TSV. 
     
     
       7. The method of  claim 6  further comprising etching the passivation layer to expose ends of the first TSV and the second TSV. 
     
     
       8. The method of  claim 1 , wherein the second TSV comprises forming the second TSV having a top-view shape of a cross, rectangle, or combination thereof. 
     
     
       9. The method of  claim 1 , wherein forming the first TSV and the second TSV comprises forming the second TSV having a different diameter than the first TSV. 
     
     
       10. The method of  claim 1 , wherein forming the first TSV and the second TSV comprises the first TSV and the second TSV extending through the substrate by the same distance. 
     
     
       11. A method comprising:
 depositing a first dielectric layer over a front side of a substrate; 
 forming a plurality of first through-substrate vias (TSVs) and a plurality of second TSVs in the first dielectric layer and the substrate, wherein the forming of the plurality of first and second TSVs comprises simultaneously patterning openings for the plurality of first TSVs and second TSVs using a single lithography mask; 
 forming an interconnect structure over the first dielectric layer; 
 grinding a back side of the substrate to expose the plurality of first TSVs and the plurality of second TSVs; and 
 forming conductive features on the back side of the substrate, wherein each of the conductive features is electrically coupled to the interconnect structure through a corresponding one of the plurality of first TSVs, and wherein each of the plurality of second TSVs is electrically isolated from the conductive features and the interconnect structure. 
 
     
     
       12. The method of  claim 11 , further comprising positioning the conductive features using the plurality of second TSVs as an alignment mark. 
     
     
       13. The method of  claim 11 , wherein first ones of the plurality of second TSVs are disposed along a first axis, second ones of the plurality of second TSVs are disposed along a second axis, wherein the first axis and the second axis are parallel to the back side of the substrate. 
     
     
       14. The method of  claim 11 , wherein the conductive features comprise a redistribution line or a metal bump. 
     
     
       15. The method of  claim 11 , further comprising forming an active device on the front side of the substrate. 
     
     
       16. The method of  claim 11  further comprising forming metal bumps over the interconnect structure, wherein each of the metal bumps is electrically connected to a corresponding one of the conductive features. 
     
     
       17. A method comprising:
 forming a functional through-substrate via (TSV) and an alignment TSV in a substrate; 
 forming an interconnect structure on a first surface of the substrate, wherein the interconnect structure comprises an alignment mark that is formed in a metal layer of the interconnect structure; 
 recessing a second surface of the substrate such that the functional TSV and the alignment TSV protrude beyond the second surface of the substrate; 
 forming a passivation layer over the second surface of the substrate, wherein the functional TSV and the alignment TSV extend through the passivation layer; and 
 forming a conductive feature on an opposite side of the substrate as the interconnect structure, the conductive feature electrically connected to the interconnect structure through the functional TSV, wherein forming the conductive feature comprises using a position of the alignment TSV as a reference. 
 
     
     
       18. The method of  claim 17  wherein the alignment mark is aligned to the alignment TSV. 
     
     
       19. The method of  claim 17 , wherein recessing the second surface of the substrate comprises etching the second surface of the substrate. 
     
     
       20. The method of  claim 17 , wherein the functional TSV and the alignment TSV are formed simultaneously.