Semiconductor structure with improved source drain epitaxy

Abstract

A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch that is smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins, second gate structures engaging the second fins, first epitaxial semiconductor features adjacent the first gate structures, and second epitaxial semiconductor features adjacent the second gate structures. The first epitaxial semiconductor features are partially embedded in the first fins at a first depth, and the second epitaxial semiconductor features are partially embedded in the second fins at a second depth that is smaller than the first depth.

What is claimed is: 
     
       1. A semiconductor structure, comprising:
 a substrate; 
 first fins extending from the substrate, the first fins having a first fin pitch; 
 second fins extending from the substrate, the second fins having a second fin pitch that is smaller than the first fin pitch; 
 first gate structures over the substrate and engaging the first fins; 
 second gate structures over the substrate and engaging the second fins; 
 first epitaxial semiconductor features adjacent the first gate structures; and 
 second epitaxial semiconductor features adjacent the second gate structures, 
 wherein the first epitaxial semiconductor features are partially embedded in the first fins at a first depth, wherein the second epitaxial semiconductor features are partially embedded in the second fins at a second depth that is smaller than the first depth. 
 
     
     
       2. The semiconductor structure of  claim 1 , wherein the first gate structures have a first gate pitch, wherein the second gate structures have a second gate pitch that is smaller than the first gate pitch. 
     
     
       3. The semiconductor structure of  claim 1 , wherein a first proximity of the first epitaxial semiconductor features to the respective first gate structures is smaller than a second proximity of the second epitaxial semiconductor features to the respective second gate structures. 
     
     
       4. The semiconductor structure of  claim 3 , wherein the first proximity ranges from about 3 nm to about 6 nm, and the second proximity ranges from about 5 nm to about 8 nm. 
     
     
       5. The semiconductor structure of  claim 1 , wherein the second depth is smaller than the first depth by at least 15 nm. 
     
     
       6. The semiconductor structure of  claim 1 , wherein the first epitaxial semiconductor features are source and drain (S/D) features of logic devices and the second epitaxial semiconductor features are S/D features of memory devices. 
     
     
       7. The semiconductor structure of  claim 1 , wherein the first and second epitaxial semiconductor features are raised above a top surface of the substrate. 
     
     
       8. The semiconductor structure of  claim 1 , further comprising:
 spacers on sidewalls of the first and second gate structures, 
 wherein a first lateral distance between the first epitaxial semiconductor features and the spacers on the sidewalls of the respective first gate structures is smaller than a second lateral distance between the second epitaxial semiconductor features and the spacers on the sidewalls of the respective second gate structures. 
 
     
     
       9. The semiconductor structure of  claim 1 , wherein one of the first epitaxial semiconductor features has a greater volume than one of the second epitaxial semiconductor features. 
     
     
       10. The semiconductor structure of  claim 1 , wherein the first epitaxial semiconductor features and the second epitaxial semiconductor features include a same semiconductor material. 
     
     
       11. A semiconductor structure, comprising:
 a first region, 
 wherein the first region includes: 
 first fins separate one from another and adjacent to each other and second fins separate one from another and adjacent to each other, the first fins being further away from each other than the second fins; 
 first gate structures engaging the first fins and second gate structures engaging the second fins; and 
 first epitaxial semiconductor features proximate the first gate structures and second epitaxial semiconductor features proximate the second gate structures, 
 wherein a first distance from the first epitaxial semiconductor features to the respective first gate structures is smaller than a second distance from the second epitaxial semiconductor features to the respective second gate structures. 
 
     
     
       12. The semiconductor structure of  claim 11 , wherein the first gate structures are further away from each other than the second gate structures. 
     
     
       13. The semiconductor structure of  claim 11 , wherein a bottom surface of the first epitaxial semiconductor features is lower than a bottom surface of the second epitaxial semiconductor features. 
     
     
       14. The semiconductor structure of  claim 11 , further comprising:
 a second region, wherein the first and second regions include transistors of opposite conductivity types, 
 wherein the second region includes: 
 third fins separate one from another and adjacent to each other and fourth fins separate one from another and adjacent to each other, the third fins being further away from each other than the fourth fins; 
 third gate structures engaging the third fins and fourth gate structures engaging the fourth fins; and 
 third epitaxial semiconductor features proximate the third gate structures and fourth epitaxial semiconductor features proximate the fourth gate structures, 
 wherein a third distance from the third epitaxial semiconductor features to the respective third gate structures is smaller than a fourth distance from the fourth epitaxial semiconductor features to the respective fourth gate structures. 
 
     
     
       15. The semiconductor structure of  claim 14 , wherein the third gate structures are further away from each other than the fourth gate structures. 
     
     
       16. The semiconductor structure of  claim 14 , wherein a bottom surface of the third epitaxial semiconductor features is lower than a bottom surface of the fourth epitaxial semiconductor features. 
     
     
       17. A semiconductor structure, comprising:
 first semiconductor fins adjacent to each other; 
 second semiconductor fins adjacent to each other, the first semiconductor fins being more sparsely distributed than the second semiconductor fins; 
 first gate structures over the first semiconductor fins; 
 second gate structures over the second semiconductor fins; 
 first gate spacers on sidewalls of the first gate structures; 
 second gate spacers on sidewalls of the second gate structures; 
 first epitaxial semiconductor features grown over the first semiconductor fins and adjacent the first gate spacers; and 
 second epitaxial semiconductor features grown over the second semiconductor fins and adjacent the second gate spacers, wherein one of the first epitaxial semiconductor features has a greater volume than one of the second epitaxial semiconductor features. 
 
     
     
       18. The semiconductor structure of  claim 17 , wherein the first gate structures are more sparsely distributed than the second gate structures. 
     
     
       19. The semiconductor structure of  claim 17 , further comprising a dielectric material filling in space between the first epitaxial semiconductor features and the respective first gate spacers and space between the second epitaxial semiconductor features and the respective second gate spacers. 
     
     
       20. The semiconductor structure of  claim 17 , wherein the first and second epitaxial semiconductor features include n-type doped silicon or p-type doped silicon germanium.