Hybrid wafer dicing approach using a split beam laser scribing process and plasma etch process

Abstract

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a split laser beam laser scribing process, such as a split shaped laser beam laser scribing process, to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

What is claimed is: 
     
       1. A system for dicing a semiconductor wafer comprising a plurality of integrated circuits, the system comprising:
 a laser scribe apparatus comprising a laser assembly configured to provide a split shaped laser beam, wherein the split shaped laser beam laser scribing comprises a one-to-two split beam running at approximately 800 kHz with an approximately 6 μj pulse energy per split beam and an approximately 800 mm/sec stage speed; and 
 a plasma etch chamber coupled to the laser scribe apparatus. 
 
     
     
       2. The system of  claim 1 , wherein the laser assembly is configured to provide the split shaped laser beam as a symmetrically split laser beam. 
     
     
       3. The system of  claim 2 , wherein the laser beam is a femto-second based laser beam. 
     
     
       4. The system of  claim 1 , wherein the laser assembly is configured to provide the split shaped laser beam as an asymmetrically split laser beam. 
     
     
       5. The system of  claim 4 , wherein the laser beam is a femto-second based laser beam. 
     
     
       6. The system of  claim 1 , wherein the laser assembly is configured to provide the split shaped laser beam as a line shaped flat top beam profile. 
     
     
       7. The system of  claim 1 , wherein the plasma etch chamber is configured for performing a deep silicon etch process, the system further comprising:
 a second plasma etch chamber coupled with the factory interface, the second plasma etch chamber configured for performing a plasma-based cleaning process.