Negative-capacitance field effect transistor

Abstract

Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a substrate; 
 a fin extending from the substrate and having a pair of source/drain features and a channel region disposed between the pair of source/drain features; 
 a first ferroelectric layer along sidewalls of the channel region of the fin and on a top surface of the substrate; 
 an isolation feature disposed over the substrate and alongside the fin such that the fin extends above the isolation feature; 
 an interfacial layer over the first ferroelectric layer; 
 a second ferroelectric layer over the interfacial layer; and 
 a gate electrode disposed on the second ferroelectric layer 
 wherein a bottom surface of the isolation feature is spaced apart from the top surface of the substrate by the first ferroelectric layer. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the first ferroelectric layer and the second ferroelectric layer are in physical contact with the isolation feature. 
     
     
       3. The semiconductor device of  claim 1 , wherein a portion of the first ferroelectric layer is disposed on the substrate. 
     
     
       4. The semiconductor device of  claim 1 , wherein a portion of the isolation feature is disposed between the first ferroelectric layer and the second ferroelectric layer along a vertical direction. 
     
     
       5. The semiconductor device of  claim 1 , wherein a composition of the first ferroelectric layer is different from a composition of the second ferroelectric layer. 
     
     
       6. The semiconductor device of  claim 1 , the first ferroelectric layer comprises indium selenide (In 2 Se 3 ) or copper indium thiophosphate (CuInP 2 S 6 ). 
     
     
       7. The semiconductor device of  claim 1 , the second ferroelectric layer comprises a metal oxide. 
     
     
       8. The semiconductor device of  claim 7 , the second ferroelectric layer comprises hafnium oxide, hafnium yttrium oxide, hafnium strontium oxide, hafnium gadolinium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium aluminum oxide, barium titanium oxide, aluminum oxide, titanium oxide, lanthanum oxide, barium strontium titanium oxide, or lead zirconium titanium oxide. 
     
     
       9. The semiconductor device of  claim 1 , wherein the gate electrode is spaced apart from the isolation feature by the first ferroelectric layer. 
     
     
       10. A device, comprising:
 a first source/drain feature and a second source/drain feature over a substrate; 
 a semiconductor fin extending between the first source/drain feature and the second source/drain feature; 
 a first ferroelectric layer disposed over sidewalls of the semiconductor fin and a top surface of the substrate; 
 an isolation feature disposed over the substrate such that the isolation feature is spaced apart from the top surface of the substrate and sidewalls of the semiconductor fin by the first ferroelectric layer; 
 a first gate spacer and a second gate spacer disposed over the first ferroelectric layer; 
 an interfacial layer disposed between the first gate spacer and the second gate spacer and in contact with the first ferroelectric layer; 
 a second ferroelectric layer disposed over the interfacial layer; and 
 a gate electrode disposed over the second ferroelectric layer. 
 
     
     
       11. The device of  claim 10 , wherein the first ferroelectric layer extends between the first source/drain feature and the second source/drain feature such that sidewalls of the first ferroelectric layer are in direct contact with the first source/drain feature and the second source/drain feature. 
     
     
       12. The device of  claim 10 , wherein a composition of the first ferroelectric layer is different from a composition of the second ferroelectric layer. 
     
     
       13. The device of  claim 12 , the first ferroelectric layer comprises indium selenide (In 2 Se 3 ) or copper indium thiophosphate (CuInP 2 S 6 ). 
     
     
       14. The device of  claim 12 , the second ferroelectric layer comprises a metal oxide. 
     
     
       15. The device of  claim 10 , wherein the first gate spacer and the second gate spacer extend along sidewalls of the interfacial layer and the second ferroelectric layer. 
     
     
       16. A structure, comprising:
 a semiconductor fin; 
 a first ferroelectric layer disposed over the semiconductor fin; 
 a first gate spacer and a second gate spacer disposed over the first ferroelectric layer; 
 an interfacial layer disposed between the first gate spacer and the second gate spacer and in contact with the first ferroelectric layer; 
 a second ferroelectric layer disposed over the interfacial layer; and 
 a gate electrode disposed directly on the second ferroelectric layer, 
 wherein a composition of the first ferroelectric layer is different from a composition of the second ferroelectric layer. 
 
     
     
       17. The structure of  claim 16 , the first ferroelectric layer comprises indium selenide (In 2 Se 3 ) or copper indium thiophosphate (CuInP 2 S 6 ). 
     
     
       18. The structure of  claim 16 , the second ferroelectric layer comprises a metal oxide. 
     
     
       19. The structure of  claim 18 , the second ferroelectric layer comprises hafnium oxide, hafnium yttrium oxide, hafnium strontium oxide, hafnium gadolinium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium aluminum oxide, barium titanium oxide, aluminum oxide, titanium oxide, lanthanum oxide, barium strontium titanium oxide, or lead zirconium titanium oxide. 
     
     
       20. The structure of  claim 16 , wherein the first gate spacer and the second gate spacer are in direct contact with the first ferroelectric layer, the interfacial layer, and the second ferroelectric layer.