Semiconductor device including an epitaxy region

Abstract

An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

What is claimed is: 
     
       1. An integrated circuit device comprising:
 a first gate stack and a second gate stack disposed over a substrate; 
 a first silicon carbonitride (SiCN) spacer liner, a second SiCN spacer liner, a third SiCN spacer liner, and a fourth SiCN spacer liner, wherein the first SiCN spacer liner and the second SiCN spacer liner are disposed adjacent to respective sidewalls of the first gate stack and the third SiCN spacer liner and the fourth SiCN spacer liner are disposed adjacent to respective sidewalls of the second gate stack; 
 a first source/drain epitaxy region, a second source/drain epitaxy region, a third source/drain epitaxy region, and a fourth source/drain epitaxy region disposed over the substrate, wherein the first gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region, the second gate stack is disposed between the third source/drain epitaxy region and the fourth source/drain epitaxy region, the first source/drain epitaxy region and the second source/drain epitaxy region have a first profile, and the third source/drain epitaxy region and the fourth source/drain epitaxy region have a second profile; 
 an interlayer dielectric (ILD) layer disposed over the substrate, the first gate stack, the second gate stack, the first SiCN spacer liner, the second SiCN spacer liner, the third SiCN spacer liner, the fourth SiCN spacer liner, the first source/drain epitaxy region, the second source/drain epitaxy region, the third source/drain epitaxy region, and the fourth source/drain epitaxy region; 
 a shallow trench isolation structure disposed within the substrate between the second source/drain epitaxy region and the third source/drain epitaxy region; 
 wherein the second SiCN spacer liner has a first surface, a second surface, and a third surface, wherein the first surface and the second surface extend substantially along a first direction, the first surface is opposite the second surface, the first surface shares a first interface with a respective sidewall of the first gate stack, the second surface shares a second interface with the ILD layer, and the third surface shares a third interface with the second source/drain epitaxy region; 
 wherein the second SiCN spacer liner further has a fourth surface extending from the first surface to the second surface and a fifth surface extending orthogonally from the second surface away from the first gate stack to the third surface, wherein the second surface extends from the fourth surface to the fifth surface; 
 wherein the third SiCN spacer liner has a sixth surface, a seventh surface, and an eighth surface, wherein the sixth surface and the seventh surface extend substantially along the first direction, the sixth surface is opposite the seventh surface, the sixth surface shares a fourth interface with a respective sidewall of the second gate stack, the seventh surface shares a fifth interface with the ILD layer, and the eighth surface shares a sixth interface with the third source/drain epitaxy region; 
 wherein the third SiCN spacer liner further has a ninth surface extending from the sixth surface to the seventh surface and a tenth surface extending orthogonally from the seventh surface away from the second gate stack to the eighth surface, wherein the seventh surface extends from the ninth surface to the tenth surface; 
 wherein a top surface of the ILD layer, a top surface of the first gate stack, a top surface of the second gate stack, the fourth surface of the second SiCN spacer liner, and the ninth surface of the third SiCN spacer liner form a common surface; 
 wherein the ILD layer physically contacts an entirety of the second surface of the second SiCN spacer liner and an entirety of the seventh surface of the third SiCN spacer liner; 
 wherein a portion of the ILD layer extends continuously from the second surface of the second SiCN spacer liner over the second source/drain epitaxy region, the shallow trench isolation structure, and the third source/drain epitaxy region to physically contact the seventh surface of the third SiCN spacer liner; and 
 wherein the portion of the ILD layer fills a first gap between a sidewall of the second source/drain epitaxy region and the second surface of the second SiCN spacer liner and a second gap between a sidewall of the third source/drain epitaxy region and the seventh surface of the third SiCN spacer liner, wherein a first aspect ratio of the first gap is different than a second aspect ratio of the second gap. 
 
     
     
       2. The integrated circuit device of  claim 1 , wherein a thickness of the first SiCN spacer liner, the second SiCN spacer liner, the third SiCN spacer liner, and the fourth SiCN spacer liner is greater than approximately 0 Angstroms and less than approximately 100 Angstroms. 
     
     
       3. The integrated circuit device of  claim 1 , wherein the first source/drain epitaxy region and the second source/drain epitaxy region include silicon and the third source/drain epitaxy region and the fourth source/drain epitaxy region include silicon and germanium. 
     
     
       4. The integrated circuit device of  claim 1 , further comprising first lightly doped source/drain (LDD) regions and second LDD regions disposed in the substrate, wherein:
 the first source/drain epitaxy region and the second source/drain epitaxy region are disposed on the first LDD regions and the third source/drain epitaxy region and the fourth source/drain epitaxy region are disposed on the second LDD regions; and 
 the second SiCN spacer liner further has an eleventh surface opposite the fifth surface and the third SiCN spacer liner has a twelfth surface opposite the tenth surface, wherein the eleventh surface extends orthogonally from the first surface away from the first gate stack and over a respective first LDD region, the twelfth surface extends orthogonally from the sixth surface away from the second gate stack and over a respective second LDD region, and the eleventh surface of the second SiCN spacer liner and the twelfth surface of the third SiCN spacer liner physically contact the respective first LDD region and the respective second LDD region, respectively. 
 
     
     
       5. The integrated circuit device of  claim 4 , wherein a top surface of the second source/drain epitaxy region is above the fifth surface of the second SiCN spacer liner and a top surface of the third source/drain epitaxy region is above the tenth surface. 
     
     
       6. The integrated circuit device of  claim 1 , further comprising source/drain contacts that extend through the ILD layer to the second source/drain epitaxy region and the third source/drain epitaxy region, respectively, wherein the source/drain contacts include metal silicide features. 
     
     
       7. The integrated circuit device of  claim 1 , wherein a bottom surface of the ILD layer is below a top surface of the second source/drain epitaxy region and a top surface of the third source/drain epitaxy region. 
     
     
       8. An integrated circuit device comprising:
 a gate stack disposed over a substrate; 
 a first L-shaped spacer having a first surface disposed along a first sidewall of the gate stack and a second L-shaped spacer having a first surface disposed along a second sidewall of the gate stack, wherein the first L-shaped spacer and the second L-shaped spacer include silicon and carbon; 
 a shallow trench isolation structure disposed within the substrate; 
 a first source/drain epitaxy region and a second source/drain epitaxy region disposed over the substrate, wherein the gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region, the first source/drain epitaxy region has a first top surface disposed between a second sidewall surface and a third sidewall surface, the second source/drain epitaxy region has a second top surface disposed between a fourth sidewall surface and a fifth sidewall surface, and the first source/drain epitaxy region and the second source/drain epitaxy region are semiconductor layers; 
 an interlayer dielectric (ILD) layer disposed over the substrate; 
 wherein a second surface of the first L-shaped spacer is opposite the first surface of the first L-shaped spacer and a second surface of the second L-shaped spacer is opposite the first surface of the second L-shaped spacer; 
 wherein a third surface of the first L-shaped spacer extends from the first surface of the first L-shaped spacer to the second surface of the first L-shaped spacer, a fourth surface of the first L-shaped spacer extends from the second surface of the first L-shaped spacer away from the gate stack to the second sidewall surface of the first source/drain epitaxy region, and the second surface of the first L-shaped spacer extends from the third surface of the first L-shaped spacer to the fourth surface of the first L-shaped spacer; 
 wherein a third surface of the second L-shaped spacer extends from the first surface of the second L-shaped spacer to the second surface of the second L-shaped spacer, a fourth surface of the second L-shaped spacer extends from the second surface of the second L-shaped spacer away from the gate stack to the fourth sidewall surface of the second source/drain epitaxy region, and the second surface of the second L-shaped spacer extends from the third surface of the second L-shaped spacer to the fourth surface of the second L-shaped spacer; 
 wherein a top surface of the gate stack, the third surface of the first L-shaped spacer, and the third surface of the second L-shaped spacer are free of the ILD layer; 
 wherein the first top surface of the first source/drain epitaxy region is higher than the fourth surface of the first L-shaped spacer and the second top surface of the second source/drain epitaxy region is higher than the fourth surface of the second L-shaped spacer; 
 wherein a first portion of the ILD layer physically contacts the first top surface, the second sidewall surface, and the third sidewall surface of the first source/drain epitaxy region, the first portion of the ILD layer extends from the second surface of the first L-shaped spacer to the second sidewall surface of the first source/drain epitaxy region, and the first portion of the ILD layer extends below the first top surface of the first source/drain epitaxy region and covers the fourth surface of the first L-shaped spacer; 
 wherein a second portion of the ILD layer physically contacts the second top surface, the fourth sidewall surface, and the fifth sidewall surface of the second source/drain epitaxy region, the second portion of the ILD layer extends from the second surface of the second L-shaped spacer to the fourth sidewall surface of the second source/drain epitaxy region, and the second portion of the ILD layer extends below the second top surface of the second source/drain epitaxy region and covers the fourth surface of the second L-shaped spacer; 
 wherein the ILD layer directly contacts an entirety of the second surface of the first L-shaped spacer, an entirety of the second surface of the second L-shaped spacer, an entirety of the fourth surface of the first L-shaped spacer, and an entirety of the fourth surface of the second L-shaped spacer; and 
 wherein the ILD layer extends continuously from the shallow trench isolation structure to physically contact the second surface of the first L-shaped spacer. 
 
     
     
       9. The integrated circuit device of  claim 8 , further comprising a first lightly doped source and drain (LDD) region and a second LDD region disposed in the substrate, wherein the gate stack is disposed between the first LDD region and the second LDD region. 
     
     
       10. The integrated circuit device of  claim 9 , wherein the first L-shaped spacer is disposed directly on a portion of the first LDD region and the second L-shaped spacer is disposed directly on a portion of the second LDD region. 
     
     
       11. The integrated circuit device of  claim 8 , wherein the first L-shaped spacer and the second L-shaped spacer further include nitrogen. 
     
     
       12. The integrated circuit device of  claim 8 , wherein:
 a first portion of the ILD layer that directly contacts the entirety of the fourth surface of the first L-shaped spacer is not connected to a second portion of the ILD layer that directly contacts the entirety of the fourth surface of the second L-shaped spacer. 
 
     
     
       13. The integrated circuit device of  claim 8 , further comprising:
 a first contact and a second contact that extend through the ILD layer respectively to the first source/drain epitaxy region and the second source/drain epitaxy region; and 
 a third contact to the gate stack. 
 
     
     
       14. The integrated circuit device of  claim 8 , wherein the first L-shaped spacer and the second L-shaped spacer each include a substantially uniform thickness. 
     
     
       15. The integrated circuit device of  claim 8 , wherein a height of a top surface of the ILD layer relative to a top surface of the substrate is about equal to a height of the top surface of the gate stack relative to the top surface of the substrate. 
     
     
       16. An integrated circuit device comprising:
 a first high-k/metal gate stack disposed between first raised source/drain epitaxy features, wherein the first high-k/metal gate stack and the first raised source/drain epitaxy features are disposed over a substrate; 
 a second high-k/metal gate stack disposed between second raised source/drain epitaxy features, wherein the second high-k/metal gate stack and the second raised source/drain epitaxy features are disposed over the substrate; 
 a shallow trench isolation structure disposed within the substrate; 
 first L-shaped spacer liners disposed along sidewalls of the first high-k/metal gate stack and second L-shaped spacer liners disposed along sidewalls of the second high-k/metal gate stack, wherein each of the first L-shaped spacer liners and the second L-shaped spacer liners has a first sidewall surface interfacing with a respective sidewall of the first high-k/metal gate stack or the second high-k/metal gate stack, a second sidewall surface that opposes the first sidewall surface and extends to a same height as the first sidewall surface, a first top surface extending from the first sidewall surface to the second sidewall surface, a second top surface extending orthogonally from the second sidewall surface to a respective one of the first raised source/drain epitaxy features or the second raised source/drain epitaxy features, and a third sidewall surface extending from the second top surface to the substrate, wherein the second sidewall surface extends from the first top surface to the second top surface; 
 a dielectric layer disposed over the substrate, wherein the dielectric layer directly contacts the first raised source/drain epitaxy features, the second raised source/drain epitaxy features, the first L-shaped spacer liners, the second L-shaped spacer liners, and the shallow trench isolation structure, wherein the first top surfaces of the first L-shaped spacer liners and the second L-shaped spacer liners are free of the dielectric layer and the dielectric layer covers an entirety of the second sidewall surfaces of the first L-shaped spacer liners and the second L-shaped spacer liners and an entirety of the second top surfaces of the first L-shaped spacer liners and the second L-shaped spacer liners; 
 wherein first portions of the dielectric layer fill first gaps between the first L-shaped spacer liners and the first raised source/drain epitaxy features; 
 wherein second portions of the dielectric layer fill second gaps between the second L-shaped spacer liners and the second raised source/drain epitaxy features; 
 wherein the first have a first depth and a first width, the first depth is between top surfaces of the first raised source/drain epitaxy features and the second top surfaces horizontal portions of the first L-shaped spacer liners, and the first width is between sidewall surfaces of the first raised source/drain epitaxy features and the second sidewall surfaces of the first L-shaped spacer liners; 
 wherein the second gaps have a second depth and a second width, the second depth is between top surfaces of the second raised source/drain epitaxy features and the second top surfaces of the second L-shaped spacer liners, and the second width is between sidewall surfaces of the second raised source/drain epitaxy features and the second sidewall surfaces of the second L-shaped spacer liners; and 
 wherein a first ratio of the first depth to the first width of the first gaps is different than a second ratio of the second depth to the second width of the second gaps. 
 
     
     
       17. The integrated circuit device of  claim 16 , wherein each of the first L-shaped spacer liners and the second L-shaped spacer liners has a bottom surface that opposes the second top surface, and the bottom surface extends from the first sidewall surface to a respective one of the first raised source/drain epitaxy features or the second raised source/drain epitaxy features. 
     
     
       18. The integrated circuit device of  claim 16 , wherein the first raised source/drain epitaxy features cover entireties of the third sidewall surfaces of the first L-shaped spacer liners. 
     
     
       19. The integrated circuit device of  claim 16 , wherein the first L-shaped spacer liners and the second L-shaped spacer liners includes silicon, carbon, and nitrogen. 
     
     
       20. The integrated circuit device of  claim 16 , wherein the first high-k/metal gate stack and the first raised source/drain epitaxy features are a portion of a p-type transistor and the second high-k/metal gate stack and the second raised source/drain epitaxy features are a portion of an n-type transistor.