Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

What we claim is:  
     
         1 . A semiconductor device comprising: 
 a semiconductor chip having a plurality of semiconductor elements and a plurality of external terminals formed in a main surface thereof;    an elastic layer provided on the main surface of the semiconductor chip in a manner to expose the plurality of external terminals;    an insulating tape provided on the elastic layer and having an opening to expose the plurality of external terminals, the opening being defined by an edge of the insulating tape;    a plurality of leads provided on a surface of the insulating tape,    wherein each, of the plurality of leads has a first portion disposed on the insulating tape and a second portion which extends across the edge of the insulating tape and is in the opening of the insulating tape, each of the second portions being electrically connected with a corresponding one of the external terminals; and    a plurality of bump electrodes formed on the first portions of the plurality of leads and being electrically connected to the plurality of leads, respectively,    wherein each of the plurality of leads includes a copper lead as core material thereof,    wherein the copper lead of each of the plurality of leads has gold-plating applied on its surface and    wherein a length of the second portion of each of the plurality of leads is longer than a straight line distance from the edge of the insulating tape to the corresponding one of the external terminals.    
     
     
         2 . A semiconductor device according to  claim 1 , wherein no other metallic material exists between the copper lead and the gold-plating.  
     
     
         3 . A semiconductor device according to  claim 1 , 
 wherein the plurality of leads are disposed between the elastic layer and the insulating tape, and    wherein the plurality of bump electrodes are contacting the corresponding ones of the plurality of leads via through holes formed in the insulating tape, respectively.    
     
     
         4 . A semiconductor device according to  claim 1 , wherein each of the plurality of leads is disposed to form a substantially straight line pattern in a plane view and to form a bended pattern in a sectional view.  
     
     
         5 . A semiconductor device according to  claim 1 , wherein the plurality of leads are disposed between the elastic layer and the insulating tape.  
     
     
         6 . A semiconductor device according to  claim 5 , 
 wherein each of the plurality of leads is disposed to form a substantially straight line pattern in a plane view and to form a bended pattern in a sectional view.    
     
     
         7 . A semiconductor device according to  claim 6 , wherein the plurality of bump electrodes are contacting the corresponding ones of the plurality of leads via through holes formed in the insulating tape, respectively.  
     
     
         8 . A semiconductor device according to  claim 7 , wherein no other metallic material exists between the copper lead and the gold-plating.  
     
     
         9 . A semiconductor device according to  claim 5 , wherein no other metallic material exists between the copper lead and the gold-plating.  
     
     
         10 . A semiconductor device, comprising: 
 a mounting substrate;    a first semiconductor device including a first semiconductor chip and a plurality of bump electrodes, the first semiconductor chip having a plurality of semiconductor elements on a main surface thereof, the plurality of bump electrodes being disposed on the main surface of the first semiconductor chip, and the first semiconductor device being mounted on the mounting substrate through the plurality of bump electrodes; and    a second semiconductor device including a second semiconductor chip, a sealing member and a plurality of leads, the sealing member having an upper surface, a rear surface opposite to the upper surface and a side surface between the upper and rear surfaces, the plurality of leads protruding outwardly from a side surface of the sealing member, and the second semiconductor device being mounted on the mounting substrate through the plurality of leads.    
     
     
         11 . A semiconductor device according to  claim 10 , wherein the first semiconductor chip is a semiconductor chip including a memory, and the second semiconductor chip is a semiconductor chip including a controller.  
     
     
         12 . A semiconductor device according to  claim 11 , wherein the memory in the first semiconductor chip is a dynamic random access memory.  
     
     
         13 . A semiconductor device according to  claim 10 , further comprising an elastic layer positioned between the main surface of the first semiconductor chip and the plurality of bump electrodes.  
     
     
         14 . A semiconductor device according to  claim 10 , 
 wherein the first semiconductor chip has a plurality of external terminals electrically connected to corresponding ones of the plurality of bump electrodes, respectively, and    wherein the minimum interval of the plurality of bump electrodes is wider than the minimum interval of the plurality of external terminals of the first semiconductor chip.    
     
     
         15 . A semiconductor device according to  claim 10 , 
 wherein the first semiconductor chip has a row of external terminals electrically connected to the plurality of bump electrodes, and    wherein the plurality of bump electrodes includes an array of bump electrodes at each of two opposing sides of the row of external terminals.    
     
     
         16 . A semiconductor device according to  claim 10 , wherein the mounting substrate, and the first and second devices comprise a memory card.  
     
     
         17 . A semiconductor device according to  claim 10 , further comprising a third semiconductor device, the third semiconductor device including a third semiconductor chip and a plurality of bump electrodes, the third semiconductor chip having a plurality of semiconductor elements on a main surface thereof, the plurality of bump electrodes being disposed on the main surface of the third semiconductor chip, and the third semiconductor device being mounted on the mounting substrate through the plurality of bump electrodes.  
     
     
         18 . A semiconductor device according to  claim 17 , wherein the first semiconductor chip and the third semiconductor chip are semiconductor chips including a memory, respectively.  
     
     
         19 . A semiconductor device according to  claim 18 , wherein the second semiconductor chip is a semiconductor chip including a controller.  
     
     
         20 . A semiconductor device according to  claim 19 , wherein the memory in the first and in the third semiconductor chip is a dynamic random access memory, respectively.  
     
     
         21 . A semiconductor device according to  claim 18 , wherein the memory in the first and in the third semiconductor chip is a dynamic random access memory, respectively.  
     
     
         22 . A semiconductor device according to  claim 17 , 
 wherein each of the first and third semiconductor chips has a plurality of external terminals electrically connected to corresponding ones of the plurality of bump electrodes, respectively, and    wherein the minimum interval of the plurality of bump electrodes is wider than the minimum interval of the plurality of external terminals corresponding to each of the first and third semiconductor chips.    
     
     
         23 . A semiconductor device according to  claim 17 , 
 wherein each of the first and third semiconductor chips has a row of external terminals electrically connected to the plurality of bump electrodes corresponding thereto, and    wherein the plurality of bump electrodes in each of the first and third semiconductor chips includes an array of bump electrodes at each of two opposing sides of the row of external terminals thereof.    
     
     
         24 . A semiconductor device according to  claim 17 , wherein the mounting substrate, and the first, second and third semiconductor devices comprise a memory card.  
     
     
         25 . A composite device, comprising: 
 a mounting substrate having a quadrilateral shaped main surface, and external connection terminals, located at one of the four end sides thereof, to retractably mount the device to an electrical equipment;    at least one first semiconductor device each including a first semiconductor chip and a plurality of bump electrodes, the first semiconductor chip having a plurality of semiconductor elements on a main surface thereof, the plurality of bump electrodes being disposed on the main surface of the first semiconductor chip, and the first semiconductor device being mounted on the mounting substrate through the plurality of bump electrodes; and    a second semiconductor device including a second semiconductor chip, a sealing member and a plurality of leads, the sealing member having an upper surface, a rear surface opposite to the upper surface and a side surface between the upper and rear surfaces, the plurality of leads protruding outwardly from a side surface of the sealing member, and the second semiconductor device being mounted on the mounting substrate through the plurality of leads.    
     
     
         26 . A composite device according to  claim 25 , 
 wherein each first semiconductor chip is a memory chip and the second semiconductor chip includes a controller, and    wherein the first and second semiconductor devices and mounting substrate comprise a memory card.    
     
     
         27 . A composite device, comprising: 
 a mounting substrate;    a plurality of first semiconductor devices arrayed on a main surface of the mounting substrate, each first semiconductor device including a first semiconductor chip and a plurality of bump electrodes, the first semiconductor chip having a plurality of semiconductor elements on a main surface thereof, the plurality of bump electrodes being disposed on the main surface of the first semiconductor chip, and the first semiconductor device being mounted on the mounting substrate through the plurality of bump electrodes; and    a second semiconductor device including a second semiconductor chip, a sealing member and a plurality of leads, the sealing member having an upper surface, a rear surface opposite to the upper surface and a side surface between the upper and rear surfaces, the plurality of leads protruding outwardly from a side surface of the sealing member, and the second semiconductor device being mounted on the mounting substrate through the plurality of leads.    
     
     
         28 . A composite device according to  claim 27 , 
 wherein each first semiconductor chip is a random access memory chip and the second semiconductor chip includes a controller, and    wherein the first and second semiconductor devices and mounting substrate comprise a memory card.    
     
     
         29 . A composite device according to  claim 27 , further comprising an elastic layer positioned between the main surface of each of the first semiconductor chips and the plurality of bump electrodes corresponding thereto.  
     
     
         30 . A method of manufacturing a semiconductor device comprising the steps of: 
 (a) providing a semiconductor chip having a main surface and a rear surface at an opposite side thereof, and with an electrode formed on the main surface;    (b) providing a wiring substrate having a wiring and a protruding lead connecting the wiring;    (c) arranging the wiring substrate over the main surface of the semiconductor chip;    (d) electrically connecting the protruding lead to the electrode of semiconductor chip by a pressing action of a bonding tool; and    (e) after the step of (c), making a splash angle of a tip of the protruding lead small.    
     
     
         31 . A method of manufacturing a semiconductor device according to  claim 30 , wherein in step (e), the splash angle of a tip of the protruding lead is made small by the bonding tool.  
     
     
         32 . A method of manufacturing a semiconductor device according to  claim 30 , further comprising, after step (e), a step of resin sealing the electrode of the semiconductor chip and the protruding lead by potting method of sealing resin.  
     
     
         33 . A method of manufacturing a semiconductor device according to  claim 32 , further comprising, after the resin sealing step, a step of forming a bump electrode arranged over the main surface of the semiconductor chip through the wiring.