Necked Finfet device

Abstract

A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure. Metal silicide is next formed on source/drain regions resulting in a FINFET device structure featuring a narrow channel region, and surrounded by composite insulator spacers located on the sides of the device structure.

1 . A FINFET device structure, comprising: 
 an insulator layer on a semiconductor substrate;    a silicon shape on said insulator layer, comprised with two wide silicon shapes connected by a necked, narrower silicon component, with a narrowest portion of said necked, narrower silicon component used as a FINFET channel region, located in the center of said necked, narrower silicon component;    a silicon dioxide gate insulator layer located on sides of said silicon shape;    a polysilicon gate structure traversing an insulator shape, with said polysilicon gate structure located on said narrowest portion of said necked, narrower silicon component, interfacing said silicon dioxide gate insulator layer located on both sides of said narrowest portion of said narrower silicon shape;    a source/drain region located in said two wide silicon shapes;    a composite insulator spacer on regions of said silicon shape not covered by said polysilicon gate structure, and on sides of said polysilicon gate structure; and    metal silicide on said two wide silicon shapes.    
   
   
       2 . The FINFET device structure of  claim 1 , wherein said silicon shape is comprised at a thickness between about 100 to 2000 Angstroms.  
   
   
       3 . The FINFET device structure of  claim 1 , wherein said narrowest portion of said necked, narrow silicon component, is comprised with a width between about 0.01 to 0.20 um.  
   
   
       4 . The FINFET device structure of  claim 1 , wherein the thickness of said silicon dioxide gate insulator layer, located on sides of said silicon shape, is between about 6 to 100 Angstroms.  
   
   
       5 . The FINFET device structure of  claim 1 , wherein the thickness of said polysilicon gate structure is between about 300 to 2000 Angstroms.  
   
   
       6 . The FINFET device structure of  claim 1 , wherein said composite insulator spacer is comprised with an underlying silicon oxide component at a thickness between about 50 to 200 Angstroms, and of an overlying silicon nitride component at a thickness between about 100 to 1000 Angstroms.  
   
   
       7 . The FINFET device structure of  claim 1 , wherein said metal silicide layer is comprised of either titanium silicide, tantalum silicide, tungsten silicide, cobalt silicide, or nickel silicide.