SOI-like structures in a bulk semiconductor substrate

Abstract

Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.

1 . An SOI-like structure, comprising: 
 a semiconductor substrate;    a trench in the substrate, the trench having an upper portion defined by an upper portion of a trench wall and a lower portion defined by a trench bottom and a lower portion of the trench wall;    a device site having a side thereof defined by an upper portion of the a trench wall; and    the lower portion of the trench defining a void in the substrate located at least partially under the site and communicating with the upper portion of the trench.    
   
   
       2 . The structure as in  claim 1  further comprising: 
 a liner on the upper portion of the trench.    
   
   
       3 . A transistor fabricated on the device site of  claim 1 .  
   
   
       4 . An FET fabricated on the device site of  claim 1 .  
   
   
       5 . An SOI-like structure, comprising: 
 a semiconductor substrate;    at least two trenches in the substrate, each trench having an upper portion, a lower portion, and a trench bottom, respectively,    a device site defined by upper portions of the at least two trenches; and plural voids in the substrate, each being defined by lower portions and trench bottoms of respective trenches and located partially under the site and each void communicating with a respective upper trench portion.    
   
   
       6 . The structure as in  claim 5  further comprising: 
 a liner on the upper portion of each respective trench and not on the lower portion of each respective trench wall.    
   
   
       7 . A transistor fabricated on the device site of  claim 5 .  
   
   
       8 . An FET fabricated on the device site of  claim 5.