Substrate band gap engineered multi-gate pMOS devices

Abstract

A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.

1 . A multi-gate transistor comprising: 
 a fin having an upper portion and a lower portion, said upper portion having a first band gap and said lower portion having a second band gap, said first band gap and said second band gap designed to inhibit current flow from said upper portion to said lower portion;    a gate structure having sidewalls electrically coupled with said upper portion and said lower portion; and    a substrate positioned below said fin.    
   
   
       2 . The multi-gate transistor of  claim 1  wherein said first band gap is at least 0.3 electron volts narrower than said second band gap.  
   
   
       3 . The multi-gate transistor of  claim 1  wherein said gate structure includes a top portion positioned over said fin.  
   
   
       4 . The multi-gate transistor of  claim 1  wherein said lower portion is formed from said substrate.  
   
   
       5 . The multi-gate transistor of  claim 1  wherein a source region and a drain region are contained within said upper portion.  
   
   
       6 . The multi-gate transistor of  claim 1  further comprising an insulator positioned between said fin and said substrate.  
   
   
       7 . The multi-gate transistor of  claim 2  wherein said upper portion is composed of silicon-germanium having approximately 30 atomic percent of germanium.  
   
   
       8 . The multi-gate transistor of  claim 4  wherein said second band gap is 0.4 electron volts wider than said first band gap.  
   
   
       9 . The multi-gate transistor of  claim 6  wherein said insulator is formed using a bonded semiconductor-on-insulator (SOI) technique.  
   
   
       10 . A multi-gate device comprising: 
 an upper portion having a first band gap, said upper portion configured to contain a source region and a drain region;    a lower portion having a second band gap wider than said first band gap and positioned below said upper portion to form a fin;    a gate structure having a first portion and a second portion, said first portion and second portion positioned on opposing sides of said fin and positioned to cover a portion of said upper portion and a portion of said lower portion; and    a substrate positioned below said lower portion.    
   
   
       11 . The multi-gate device of  claim 10  wherein said gate structure further comprises a third portion positioned over said upper portion.  
   
   
       12 . The multi-gate device of  claim 10  further comprising a channel region in said upper portion located between said source region and said drain region, said channel region doped to a concentration level of approximately 1×10 19  atoms/cm 3 .  
   
   
       13 . The multi-gate device of  claim 10  wherein said lower portion is formed from said substrate.  
   
   
       14 . The multi-gate device of  claim 10  further comprising an insulator between said lower portion and said substrate.  
   
   
       15 . The multi-gate device of  10  further comprising a gate insulator positioned between said gate structure and said fin.  
   
   
       16 . The multi-gate device of  claim 11  wherein said first band gap is at least 0.3 electron volts narrower than said upper portion.  
   
   
       17 . The multi-gate device of  claim 11  wherein said gate structure is formed from a metal.  
   
   
       18 . The multi-gate device of  claim 16  wherein said upper portion is formed from silicon-germanium.  
   
   
       19 . The multi-gate device of  claim 18  wherein said upper portion contains approximately 20 atomic percent of germanium.  
   
   
       20 . The multi-gate device of  claim 19  wherein said substrate is composted of silicon.  
   
   
       21 . A method comprising: 
 positioning an upper portion having a first band gap over a lower portion to form a fin over a substrate, said lower portion having a second band gap wider than said first band gap;    forming a first gate and a second gate on opposite sides of said fin, said first and said second gate formed to electrically couple with said upper portion and said lower portion; and    creating a source and drain region within said upper portion on opposite sides of a channel.    
   
   
       22 . The method of  claim 21  wherein said upper portion is formed of silicon-germanium composed of 30 atomic percent of germanium.  
   
   
       23 . The method of  claim 21  further comprising forming a third gate positioned over said fin.  
   
   
       24 . The method of  claim 21  wherein the upper portion is formed using a III-V semiconductor material such that said second band gap is at least 0.3 electron volts wider than said first band gap.  
   
   
       25 . The method of  claim 21  further comprising implanting ions below said channel to form halo implants of the same conductivity type as said channel, said halo implants having a concentration of said ions of a half order greater than said channel.  
   
   
       26 . The method of  claim 21  further comprising forming an insulating layer between said lower portion and said substrate.  
   
   
       27 . The method of  claim 23  further comprising forming a gate insulator between said gates and said fin.  
   
   
       28 . The method of  claim 23  wherein said upper portion is formed to a thickness between 200 and 2000 angstroms.  
   
   
       29 . The method of  claim 23  wherein said first gate, said second gate, and said third gate are formed from titanium nitride.  
   
   
       30 . The method of  claim 28  wherein said fin is approximately 450 angstroms thick.