Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors

Abstract

This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

1 . A method for fabricating an FET device in a semiconductor layer comprising heating said semiconductor layer to an elevated temperature, and ion implanting at said elevated temperature said FET's source/drain (S/D) regions.  
   
   
       2 . The method of  claim 1  further comprising: 
 forming a patterned masking layer before said ion implantation, said patterned masking layer defining first source/drain regions that will be subjected to said ion implantation and second substrate regions that will protected from said ion implantation and removing said patterned mask after said ion implantation.    
   
   
       3 . The method of  claim 1  wherein said semiconductor layer comprises a bulk semiconductor; a semiconductor-on-insulator layer; or a combination of bulk and semiconductor-on-insulator layers such that at least part of the semiconductor layer is bulk and at least part of the semiconductor layer is disposed on an insulator; said semiconductor layer comprising one or more of Si, SiC, Ge, GeC, SiGe, or SiGeC; these materials in layered combinations; these materials strained, partially strained, or unstrained.  
   
   
       4 . The method of  claim 1  wherein said semiconductor layer comprises a silicon-on-insulator layer with a thickness less than 30 nm.  
   
   
       5 . The method of  claim 1  wherein said FET comprises semiconductor S/D regions separated by a semiconducting channel region, said S/D regions and said channel regions comprising different semiconductor materials, said S/D regions being strained, partially strained, or unstrained.  
   
   
       6 . The method of  claim 5  wherein said semiconducting channel region comprises Si and said S/D regions comprise a strained SiGe alloy having a Ge content equal to or greater than 25 atomic percent.  
   
   
       7 . The method of  claim 5  wherein said semiconducting channel region comprises Si and said S/D regions comprise a strained SiC alloy having a C content equal to or greater than 0.5 atomic percent.  
   
   
       8 . The elevated temperature of  claim 1  comprising a temperature in the range from 70° C. to 900° C.  
   
   
       9 . The ion implantation of  claim 1  wherein the ion implanted species comprises one or more of As, B, B 1 , BF 2 , Ge, P, and Sb.  
   
   
       10 . A divided-dose-anneal-in-between (DDAB) method of ion implantation comprising 
 selecting a substrate including a semiconductor layer;    defining first semiconductor layer regions that will be subjected to at least two subsequent ion implantation steps and second semiconductor layer regions that will be protected from said at least two subsequent ion implantation steps;    subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a first ion implantation;    subjecting said substrate to a first anneal;    subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a final ion implantation; and    subjecting said substrate to a final anneal;    wherein residual damage left in said first semiconductor layer regions (as measured by strain loss and/or defect density) after the final anneal is less than the residual damage that would be left in said first semiconductor layer regions if the above process steps were performed without said first anneal.    
   
   
       11 . The method of  claim 10  further including one or more cycles of supplemental implant and annealing steps comprising 
 subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a supplemental ion implantation; and    subjecting said substrate to a supplemental anneal;    said cycles performed after the first anneal and before the final implant, wherein residual damage left in said first semiconductor layer regions (as measured by strain loss and/or defect density) after the final anneal is less than the residual damage that would be left in said first semiconductor layer regions if the above process steps were performed without said first and said supplemental annealing steps.    
   
   
       12 . The method of  claim 10  wherein a masking layer defining said first and second semiconductor layer regions is applied to the substrate before each implant step and removed from the substrate before each annealing step.  
   
   
       13 . The method of  claim 10  wherein a masking layer defining said first and second semiconductor layer regions is applied to the substrate before the first implant step and not removed from the substrate until after the final implant step.  
   
   
       14 . The method of  claim 10  wherein said semiconductor layer comprises a bulk semiconductor; a semiconductor-on-insulator layer; or a combination of bulk and semiconductor-on-insulator layers such that at least part of the semiconductor layer is bulk and at least part of the semiconductor layer is disposed on an insulator; said semiconductor layer comprising one or more of Si, SiC, Ge, GeC, SiGe, and SiGeC; these materials in layered combinations; these materials strained, partially strained, or unstrained.  
   
   
       15 . The method of  claim 10  wherein said semiconductor layer comprises a silicon-on-insulator layer with a thickness less than 30 nm.  
   
   
       16 . The method of  claim 10  wherein said FET comprises semiconductor S/D regions separated by a semiconducting channel region, said S/D regions and said channel regions comprising different semiconductor materials, said S/D regions being strained, partially strained, or unstrained.  
   
   
       17 . The method of  claim 16  wherein said semiconducting channel region comprises Si and said S/D regions comprise a strained SiGe alloy having a Ge content equal to or greater than 25 atomic percent.  
   
   
       18 . The method of  claim 16  wherein said semiconducting channel region comprises Si and said S/D regions comprise a strained SiC alloy having a C content equal to or greater than 0.5 atomic percent.  
   
   
       19 . The method of  claim 10  performed at a temperature over 150° C. and under 1350° C.  
   
   
       20 . The ion implantation of  claim 10  wherein the ion implanted species comprises one or more of As, B, B 1 , BF 2 , Ge, P, and Sb.  
   
   
       21 . A divided-dose-anneal-in-between (DDAB) method of ion implantation comprising the steps of 
 selecting a substrate including a semiconductor layer;    defining first semiconductor layer regions that will be subjected to at least two subsequent ion implantation steps and second semiconductor layer regions that will be protected from said at least two subsequent ion implantation steps;    subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a first ion implantation;    subjecting said substrate to a first anneal;    subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a final ion implantation; and    subjecting said substrate to a final anneal;    further including the steps of    applying a masking layer defining said first and second semiconductor layer regions to the substrate before the first implant step, said masking layer remaining in place until after the final implant step.    
   
   
       22 . The method of  claim 21  further including one or more cycles of supplemental implant and annealing steps comprising 
 subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a supplemental ion implantation; and    subjecting said substrate to a supplemental anneal;    said cycles performed after the first anneal and before the final implant.    
   
   
       23 . An FET device in a semiconductor layer, said FET device comprising source/drain regions subjected to ion implantation while said semiconductor-on-insulator is held at an elevated temperature.  
   
   
       24 . The FET device of  claim 23  wherein said elevated temperature is in the range from 70° C. to 900° C.  
   
   
       25 . An FET device in a semiconductor layer, said FET device comprising source/drain regions subjected to a divided-dose-anneal-in-between (DDAB) method of ion implantation comprising the steps of 
 selecting a substrate including a semiconductor layer;    defining first semiconductor layer regions that will be subjected to at least two subsequent ion implantation steps and second semiconductor layer regions that will be protected from said at least two subsequent ion implantation steps;    subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a first ion implantation;    subjecting said substrate to a first anneal;    subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a final ion implantation; and    subjecting said substrate to a final anneal;    wherein residual damage left in said first semiconductor layer regions (as measured by strain loss and/or defect density) after the final anneal is less than the residual damage that would be left in said first semiconductor layer regions if the above process steps were performed without said first anneal.    
   
   
       26 . The FET device of  claim 25  wherein said DDAB method of ion implantation further includes one or more cycles of supplemental implant and annealing steps comprising 
 subjecting said first semiconductor layer regions (but not said second semiconductor layer regions) to a supplemental ion implantation; and    subjecting said substrate to a supplemental anneal;    said cycles performed after the first anneal and before the final implant, wherein residual damage left in said first semiconductor layer regions (as measured by strain loss and/or defect density) after the final anneal is less than the residual damage that would be left in said first semiconductor layer regions if the above process steps were performed without said first and said supplemental annealing steps.    
   
   
       27 . The FET device of  claim 23  wherein said semiconductor layer comprises a bulk semiconductor; a semiconductor-on-insulator layer; or a combination of bulk and semiconductor-on-insulator layers such that at least part of the semiconductor layer is bulk and at least part of the semiconductor layer is disposed on an insulator; said semiconductor layer comprising one or more of Si, SiC, Ge, GeC, SiGe, and SiGeC; these materials in layered combinations; these materials strained, partially strained or unstrained.  
   
   
       28 . The FET device of  claim 23  wherein said semiconductor layer comprises a silicon-on-insulator layer with a thickness less than 30 nm.  
   
   
       29 . The FET device of  claim 23  wherein said FET comprises semiconductor S/D regions separated by a semiconducting channel region, said S/D regions and said channel regions comprising different semiconductor materials, said S/D regions being strained, partially strained, or unstrained.  
   
   
       30 . The FET device of  claim 29  wherein said semiconducting channel region comprises Si and said S/D regions comprise a strained SiGe alloy having a Ge content equal to or greater than 25 atomic percent.  
   
   
       31 . The FET device of  claim 29  wherein said semiconducting channel region comprises Si and said S/D regions comprise a strained SiC alloy having a C content equal to or greater than 0.5 atomic percent.