Apparatus and Method for Controlling Plasma Potential

Abstract

An apparatus is provided for semiconductor wafer plasma processing. The apparatus includes a chamber having a lower electrode and an upper electrode disposed therein. The lower electrode is defined to transmit a radiofrequency current through the chamber to generate a plasma within the chamber. The upper electrode is disposed above the lower electrode and is electrically isolated from the chamber. A voltage source is connected to the upper electrode. The voltage source is defined to control an electric potential of the upper electrode relative to the chamber. The electric potential of the upper electrode as controlled by the voltage source is capable of influencing an electric potential of the plasma to be generated between the lower and upper electrodes.

1 . An apparatus for semiconductor wafer plasma processing, comprising:
 a chamber;   a lower electrode disposed within the chamber and defined to transmit a radiofrequency current through the chamber, the lower electrode defined to support a semiconductor wafer in exposure to a plasma to be generated within the chamber by the radiofrequency current;   an upper electrode disposed above and in a spaced apart relationship with the lower electrode, wherein the upper electrode is electrically isolated from the chamber; and   a voltage source connected to the upper electrode, the voltage source defined to control an electric potential of the upper electrode relative to the chamber, wherein the electric potential of the upper electrode as controlled by the voltage source is capable of influencing an electric potential of the plasma to be generated between the lower electrode and the upper electrode.   
   
   
       2 . An apparatus for semiconductor wafer plasma processing as recited in  claim 1 , wherein the voltage source is a direct current voltage source. 
   
   
       3 . An apparatus for semiconductor wafer plasma processing as recited in  claim 1 , wherein the electric potential of the upper electrode as controlled by the voltage source is capable of reducing an electric potential of the plasma relative to the chamber, the plasma electric potential reduction enabling plasma confinement. 
   
   
       4 . An apparatus for semiconductor wafer plasma processing as recited in  claim 1 , wherein the voltage source is defined to maintain the electric potential of the upper electrode at a level less than the electric potential of the plasma. 
   
   
       5 . An apparatus for semiconductor wafer plasma processing as recited in  claim 1 , wherein the voltage source is defined to represent low impedance to the radiofrequency current to be transmitted through the chamber. 
   
   
       6 . An apparatus for semiconductor wafer plasma processing as recited in  claim 1 , wherein the upper electrode is defined by a central section and one or more annular sections disposed concentrically outside the central section, wherein adjacent sections of the upper electrode are electrically separated from each other by a dielectric material, wherein each section of the upper electrode is connected to a respective voltage source. 
   
   
       7 . An apparatus for semiconductor wafer plasma processing as recited in  claim 6 , wherein each voltage source is defined to control an electric potential of the upper electrode section to which the voltage source is connected to enable establishment of an electric potential profile across an entirety of the upper electrode. 
   
   
       8 . An apparatus for semiconductor wafer plasma processing, comprising:
 a chamber;   a lower electrode disposed within the chamber and defined to transmit a radiofrequency current through the chamber, the lower electrode defined to support a semiconductor wafer in exposure to a plasma to be generated within the chamber by the radiofrequency current;   an upper electrode disposed above and in a spaced apart relationship with the lower electrode, wherein the plasma is to be generated and confined to a volume between the lower electrode and the upper electrode; and   an impedance control device connected between a central region of the upper electrode and a reference ground, the impedance control device defined to control a radiofrequency current transmission path through the central region of the upper electrode, wherein control of the radiofrequency current transmission path enables confinement control of the plasma.   
   
   
       9 . An apparatus for semiconductor wafer plasma processing as recited in  claim 8 , wherein the impedance control device is defined to increase a low frequency impedance. 
   
   
       10 . An apparatus for semiconductor wafer plasma processing as recited in  claim 8 , wherein the impedance control device is defined to enable increased power deposition near a periphery of the upper electrode, the increased power deposition near the periphery of the upper electrode strengthening confinement of the plasma. 
   
   
       11 . An apparatus for semiconductor wafer plasma processing, comprising:
 a chamber;   a lower electrode disposed within the chamber and defined to transmit a radiofrequency current through the chamber, the lower electrode defined to support a semiconductor wafer in exposure to a plasma to be generated within the chamber by the radiofrequency current; and   an upper electrode disposed above and in a spaced apart relationship with the lower electrode, wherein the upper electrode is defined by a doped semiconductor material, wherein a doping concentration within the upper electrode varies radially from a center to a periphery of the upper electrode.   
   
   
       12 . An apparatus for semiconductor wafer plasma processing as recited in  claim 11 , wherein the doping concentration at a given location within the upper electrode is defined to control an electric resistance through the given location of the upper electrode, the electric resistance through the given location of the upper electrode capable of influencing an electric potential of the upper electrode at the given location. 
   
   
       13 . An apparatus for semiconductor wafer plasma processing as recited in  claim 11 , wherein the upper electrode is defined as a doped silicon material. 
   
   
       14 . An apparatus for semiconductor wafer plasma processing as recited in  claim 11 , wherein the upper electrode is electrically isolated from the chamber, the chamber representing an electric ground. 
   
   
       15 . An apparatus for semiconductor wafer plasma processing as recited in  claim 14 , further comprising:
 a voltage source connected to the upper electrode, the voltage source defined to control an electric potential of the upper electrode relative to the chamber.   
   
   
       16 . A method for controlling plasma confinement, comprising:
 generating a plasma within a chamber between a lower electrode and an upper electrode; and   controlling a voltage source connected between the upper electrode and the chamber such that an electric potential on the upper electrode is controlled, wherein an electric potential of the plasma responds to control of the electric potential on the upper electrode, the electric potential of the plasma affecting a confinement of the plasma within the chamber.   
   
   
       17 . A method for controlling plasma confinement as recited in  claim 16 , wherein the voltage source is a direct current voltage source having low impedance to radiofrequency current. 
   
   
       18 . A method for controlling plasma confinement as recited in  claim 16 , wherein the voltage source is controlled to cause the electric potential of the plasma to be decreased relative to the chamber, the decreased electric potential of the plasma serving to support confinement of the plasma. 
   
   
       19 . A method for controlling plasma confinement as recited in  claim 16 , further comprising:
 establishing a polarity of the voltage source such that an electric field strength between the plasma and the chamber is reduced, reduction in the electric field strength serving to support confinement of the plasma.   
   
   
       20 . A method for controlling plasma confinement as recited in  claim 16 , wherein controlling the voltage source includes independently controlling multiple voltage sources, wherein each voltage source is defined to control an electric potential of a respective section of the upper electrode to enable establishment of an electric potential profile across an entirety of the upper electrode.