Uniform critical dimension size pore for pcram application

Abstract

A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. A via is defined in the insulating layers above the intermediate insulating layer. A channel is created for etch with a sacrificial spacer. A pore is defined in the intermediate insulating layer. All insulating layers above the intermediate insulating layer are removed, and the entirety of the remaining pore is filled with phase change material. An upper electrode is formed above the phase change material.

1 . A method of forming a memory cell, the method comprising:
 forming a plurality of insulating layers over a substrate;   forming a bottom electrode within at least one of the insulating layers;   defining a via through at least one of the insulating layers above the bottom electrode, the via and bottom electrode being separated by at least one intermediate insulating layer;   forming a sacrificial spacer in the via above the intermediate insulating layer, the sacrificial spacer including a channel having a smaller diameter than a diameter of the via;   defining a pore through the intermediate insulating layer below the sacrificial spacer and above the bottom electrode such that the channel continues through the intermediate insulating layer to the bottom electrode;   removing the sacrificial spacer;   depositing phase change material in the pore, the phase change material filling the entire pore; and   forming an upper electrode above the phase change material.   
   
   
       2 . The method of  claim 1 , further comprising forming an undercut in at least one of the insulating layers, the undercut defining an overhang above the via. 
   
   
       3 . The method of  claim 1 , wherein forming the sacrificial spacer includes:
 depositing a sacrificial spacer layer within the via, the conformality of deposition of the sacrificial spacer layer being such that a cavity is formed by the sacrificial spacer layer; and   etching the sacrificial spacer layer such that the area below the cavity forms a ridge within the sacrificial spacer.   
   
   
       4 . The method of  claim 1 , wherein the pore is tubular. 
   
   
       5 . The method of  claim 1 , wherein the surface of the pore is substantially planar. 
   
   
       6 . The method of  claim 1 , wherein the side walls of the intermediate insulating layer defining the pore are substantially perpendicular to an upper surface of the intermediate insulating layer. 
   
   
       7 . The method of  claim 1 , wherein the diameter of the side walls of the intermediate insulating layer defining the pore is substantially less than the diameter of the via. 
   
   
       8 . The method of  claim 1 , further comprising:
 removing all sacrificial layers above the intermediate insulating layer prior to forming the phase change material.   
   
   
       9 . A memory cell comprising:
 a substrate;   an insulating layer formed over the substrate;   a bottom electrode formed within the insulating layer;   a pore in the insulating layer above the bottom electrode;   phase change material formed within the pore, the phase change material filling the entire pore; and   an upper electrode formed above the phase change material.   
   
   
       10 . The memory cell of  claim 9 , wherein the pore is tubular. 
   
   
       11 . The memory cell of  claim 10 , wherein the surface of the pore is substantially planar. 
   
   
       12 . The memory cell of  claim 9 , wherein the side walls of the intermediate insulating layer defining the pore are substantially perpendicular to an upper surface of the intermediate insulating layer. 
   
   
       13 . The memory cell of  claim 9 , wherein the phase change material and upper electrode are patterned for bit line connections. 
   
   
       14 . The memory cell of  claim 9 , wherein the diameter of the side walls of the intermediate insulating layer defining the pore is substantially less than the diameter of the via. 
   
   
       15 . An integrated circuit comprising one or more memory cells, at least one of the memory cells comprising:
 a substrate;   an insulating layer formed over the substrate;   a bottom electrode formed within the insulating layer;   a pore in the insulating layer above the bottom electrode;   phase change material formed within the pore, the phase change material filling the entire pore; and   an upper electrode formed above the phase change material.   
   
   
       16 . The integrated circuit of  claim 15 , wherein the pore is tubular. 
   
   
       17 . The integrated circuit of  claim 15 , wherein the pore is substantially planar. 
   
   
       18 . The integrated circuit of  claim 15 , wherein the phase change material and upper electrode are patterned for bit line connection.