Nonvolatile Memory Devices Including a Resistor Region

Abstract

Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

1 . A memory device comprising:
 a semiconductor substrate including a cell array region, a peripheral circuit region, a resistor region and a device isolation layer defining an active region;   a cell insulation layer and a cell gate electrode stacked on the semiconductor substrate in the cell array region;   a peripheral circuit gate insulation layer and a peripheral gate electrode stacked on the semiconductor substrate in the peripheral circuit region, the peripheral gate electrode including a first conductive layer and a second conductive layer on the first conductive layer; and   a resistor disposed on the device isolation layer in the resistor region, wherein the resistor includes the first conductive layer and not the second conductive layer and the cell gate electrode includes the second conductive layer and not the first conductive layer.   
     
     
         2 . The memory device of  claim 1 , wherein the memory device comprises a non-volatile memory and wherein the cell insulation layer comprises a cell tunnel insulation layer, a charge trapping layer on the cell tunnel insulation layer and a cell blocking insulation layer on the cell tunnel insulating layer and wherein the cell gate electrode is on the cell blocking insulation layer. 
     
     
         3 . The nonvolatile memory of  claim 2 , wherein the cell gate electrode further includes a third conductive layer interposed between the second conductive layer and the cell blocking insulation layer. 
     
     
         4 . The nonvolatile memory of  claim 2 , wherein the peripheral gate electrode further includes a fourth conductive layer interposed between the first conductive layer and the peripheral gate insulation layer. 
     
     
         5 . The nonvolatile memory of  claim 2 , wherein the charge trapping layer comprises a silicon nitride (Si 3 N 4 ) layer, a nanocrystalline silicon layer, a nanocrystalline silicon germanium layer, a nanocrystalline metal layer, a nanocrystalline germanium layer, a tantalum oxide (TaO or Ta 2 O 5 ) layer, an aluminum oxide (Al 2 O 3 ) layer, a hafnium oxide (HfO 2 ) layer, a hafnium aluminum oxide (HfAlO) layer and/or a hafnium silicate nitride (HFSiON) layer. 
     
     
         6 . The nonvolatile memory of  claim 2 , wherein the first conductive layer comprises impurity-doped polysilicon. 
     
     
         7 . The nonvolatile memory of  claim 4 , wherein the fourth conductive layer comprises impurity-doped polysilicon. 
     
     
         8 . The nonvolatile memory of  claim 2 , wherein the second conductive layer comprises a metal-containing layer or a bi-layer including the metal-containing layer and an impurity-doped polysilicon layer. 
     
     
         9 . The nonvolatile memory of  claim 3 , wherein the third conductive layer comprises an impurity-doped polysilicon layer, a metal-containing layer or a bi-layer including the impurity-doped polysilicon layer and the metal-containing layer. 
     
     
         10 . The nonvolatile memory of  claim 8 , wherein the metal-containing layer comprises a tantalum nitride (TaN) layer, a tantalum (Ta) layer, a tungsten silicide (WSi) layer, a cobalt silicide (CoSi) layer, a titanium silicide (TiSi) layer, a tungsten (W) layer, a tungsten nitride (WN) layer, a titanium (Ti) layer, a titanium nitride (TiN) layer, a titanium aluminum nitride (TiAlN) layer, a molybdenum (Mo) layer and/or a platinum (Pt) layer.