Mixed orientation and mixed material semiconductor-on-insulator wafer

Abstract

The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.

1 . A process for fabricating a semiconductor device, comprising:
 providing a wafer having a first semiconductor layer with a first crystalline orientation, a first insulating layer, a second semiconductor layer with a second crystalline orientation and a second insulating layer;   forming a first recess and a second recess on the second insulating layer;   epitaxially growing the second semiconductor layer to fill the first recess;   masking the filled recess; and   epitaxially growing the first semiconductor layer to fill the second recess to form a silicon-on-insulator device having the first and the second crystalline orientations.   
   
   
       2 . The process of  claim 1 , wherein the step of growing the second semiconductor layer to fill the first recess further comprises forming a via in the second insulating layer to expose a surface of the second silicon layer. 
   
   
       3 . The process of  claim 1 , wherein the step of growing the second semiconductor layer to fill the first recess further comprises removing excess silicon growth. 
   
   
       4 . The process of  claim 3 , wherein the step of removing excess growth further comprises chemical and mechanical polishing. 
   
   
       5 . The process of  claim 1 , wherein the step of growing the first semiconductor layer to fill the second recess further comprises forming via. 
   
   
       6 . The process of  claim 5 , wherein the step of growing the first semiconductor layer to fill the second recess further comprises passivating growth from the second silicon layer. 
   
   
       7 . The process of  claim 6 , wherein the step of growing the first semiconductor layer to fill the second recess further comprises exposing a surface of the first semiconductor layer to crystalline growth. 
   
   
       8 . The process of  claim 1 , wherein growing the first or the second semiconductor layer further comprises epitaxial growing. 
   
   
       9 . The process of  claim 1 , wherein each of the first semiconductor layer and the second semiconductor layer defines a different semiconductor material. 
   
   
       10 . A microprocessor having a plurality of silicon on insulator layers prepared according to  claim 1 . 
   
   
       11 . A method for fabricating a semiconductor on an insulated wafer, comprising:
 providing a wafer having an insulator layer interposed between a first semiconductor layer with a first crystalline orientation and a second semiconductor layer with a second crystalline orientation;   exposing a surface of the first semiconductor layer by forming a via in the insulator layer and the second semiconductor layer;   masking a portion of the second semiconductor layer;   growing a first region using the first semiconductor layer as a template, the first region having the same crystalline orientation as the first semiconductor layer; and   unmasking the portion of the second semiconductor layer to form a plurality of regions, each region having one of the first or the second crystal orientation on the insulator layer.   
   
   
       12 . The method of  claim 11 , further comprising forming a trench in the grown first region to define two new regions. 
   
   
       13 . The method of  claim 11 , wherein the first semiconductor layer defines a silicon layer with (100) crystalline orientation. 
   
   
       14 . The method of  claim 11 , wherein the first semiconductor layer is SiGe. 
   
   
       15 . The method of  claim 11 , wherein the step of growing a first region further comprises epitaxially growing the first crystalline orientation. 
   
   
       16 . A microprocessor having a plurality of silicon on insulator layers prepared according to  claim 11 . 
   
   
       17 . A method for fabricating a semiconductor on insulator wafer, comprising:
 providing wafer having a first semiconductor layer with a first crystalline orientation, a first insulating layer, a second semiconductor layer and a second oxide layer,   forming a first via to expose a surface of the first semiconductor layer,   forming a second via to expose a surface of the second semiconductor layer;   epitaxially growing each of the first and the second semiconductor layers to fill the first and the second via, respectively;   depositing a first and a second regions of an amorphous semiconductor layer, the first amorphous semiconductor region in contact with the first semiconductor layer and the second amorphous semiconductor region in contact with the second semiconductor layer, and   recrystallizing the first and the second amorphous semiconductor regions to form a first semiconductor on insulator region with the first crystalline orientation and a second semiconductor on insulator region with the second crystalline orientation.   
   
   
       18 . The method of  claim 17 , wherein the step of forming a via further comprises masking an exposed portion of the second semiconductor layer. 
   
   
       19 . The method of  claim 18 , wherein each of the first and the second amorphous semiconductor regions defines a discrete region. 
   
   
       20 . The method of  claim 18 , wherein each of the first and the second semiconductor layers defines a different semiconductor material. 
   
   
       21 . A microprocessor device fabricated according to  claim 11 . 
   
   
       22 . A method for fabricating a semiconductor on an insulated wafer, comprising:
 providing a substrate having a first lattice constant and an insulator layer deposited thereon, the insulator layer defining a plurality of recessed cavities and at least one via exposing a surface of the substrate;   epitaxially growing a first semiconductor layer having a second lattice constant to fill the plurality of recessed cavities and the at least one via to form a plurality of filled cavities and a filled via; and   selectively and epitaxially growing a second semiconductor layer over the filled cavities to form a second semiconductor layer, wherein the second semiconductor layer is strained relative to the substrate.   
   
   
       23 . The method of  claim 22 , wherein the first in-plane lattice constant and the second in-plane lattice constant are substantially similar. 
   
   
       24 . The method of  claim 22 , wherein the step of selectively and epitaxially growing a second semiconductor layer further comprises growing a second semiconductor layer over the at least one filled via. 
   
   
       25 . The method of  claim 22 , wherein the second semiconductor layer provides enhanced carrier mobility. 
   
   
       26 . The method of  claim 22 , wherein the second semiconductor layer further comprises a third lattice constant, the third lattice constant under tensile strain relative to at least one of the first lattice constant or the second lattice constant. 
   
   
       27 . The method of  claim 22 , wherein the second semiconductor layer ( 57 ) is under tensile strain relative to the crystalline structure of the first semiconductor layer. 
   
   
       28 . A microprocessor device fabricated according to  claim 22 . 
   
   
       29 . A semiconductor device comprising:
 a substrate having thereon a first insulated region and a second insulated region, the first insulated region having a first semiconductor material with a first lattice constant and the second insulated region having a second semiconductor material with a second lattice constant;   wherein the first semiconductor material has a crystalline strain relative to the second semiconductor material.   
   
   
       30 . The semiconductor device of  claim 29 , further comprising an oxide layer interposed between the substrate and at least one of the first or second insulated regions. 
   
   
       31 . The semiconductor device of  claim 29 , wherein the first lattice constant and the second lattice constant define different crystalline orientations. 
   
   
       32 . The semiconductor device of  claim 29 , wherein the first semiconductor material and the second semiconductor material have dissimilar crystalline orientations. 
   
   
       33 . The semiconductor device of  claim 29 , further comprising an intermediate layer having a first crystalline orientation interposed between the substrate and at least one of the first or the second insulate layers. 
   
   
       34 . The semiconductor device of  claim 33 , wherein the intermediate layer includes the first semiconductor material. 
   
   
       35 . A semiconductor device comprising a handle having formed thereon a first insulated region and a second insulated region; each of the first and the second insulated regions respectively including a first and a second semiconductor regions; the first semiconductor region having a first lattice constant; the second semiconductor region having a second lattice constant, the second semiconductor region having a tensile strain relative to the first semiconductor region. 
   
   
       36 . The semiconductor device of  claim 35 , wherein the first and the second semiconductor regions have substantially similar crystalline configurations. 
   
   
       37 . The semiconductor device of  claim 35 , wherein the first and the second semiconductor regions have a different crystalline configuration. 
   
   
       38 . The semiconductor device of  claim 35 , wherein the second semiconductor region has dissimilar in-plane and out-of-plane lattice constants. 
   
   
       39 . The semiconductor device of  claim 35 , wherein the first semiconductor region has substantially similar in-plane and out-of-plane lattice constants.