Method of Forming Phase Change Memory Cell With Reduced Switchable Volume

Abstract

A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.

1 . A method of forming a memory cell, the method comprising the steps of:
 forming a dielectric layer;   patterning a hole in the dielectric layer by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material; and   forming a phase change feature in contact with dielectric layer, a portion of the phase change feature at least partially filling the hole in the dielectric layer;   wherein at least a portion of the patterned dielectric layer remains in the ultimate memory cell.   
   
   
       2 . The method of  claim 1 , wherein a fraction of the phase change feature is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal to the memory cell. 
   
   
       3 . The memory cell of  claim 2 , wherein the fraction of the phase change material operative to switch between lower and higher electrical resistance states is substantially located within the hole in the dielectric layer. 
   
   
       4 . The memory cell of  claim 1 , wherein the average width of the hole in the dielectric layer is less than a prescribed minimum lithographic dimension. 
   
   
       5 . The method of  claim 1 , further comprising the steps of forming an electrode, the electrode contacting the portion of the phase change feature at least partially filling the hole in the dielectric layer. 
   
   
       6 . The method of  claim 1 , wherein the dielectric layer comprises silicon dioxide. 
   
   
       7 . The method of  claim 1 , wherein the catalytic material comprises at least one material selected from Group IVB, VB, VIB, VIIB, and VIII of the Periodic Table of the Elements. 
   
   
       8 . The method of  claim 1 , wherein the catalytic material comprises platinum. 
   
   
       9 . The method of  claim 1 , wherein the catalytic material is supported by a support comprising at least one of a glass, a metal, and a polymer. 
   
   
       10 . The method of  claim 1 , wherein the reactant comprises a liquid or a gas. 
   
   
       11 . The method of  claim 1 , wherein the reactant comprises at least one of chlorine atoms, oxygen atoms, and fluorine atoms. 
   
   
       12 . The method of  claim 1 , wherein the dielectric layer comprises silicon dioxide, the catalytic material comprises platinum, and the reactant comprises fluorine atoms. 
   
   
       13 . The method of  claim 12 , wherein the reactant comprises xenon difluoride. 
   
   
       14 . The method of  claim 1 , wherein the phase change feature comprises at least one of germanium, antimony, sulfur, selenium, and tellurium. 
   
   
       15 . The method of  claim 1 , wherein the phase change feature comprises a ternary alloy comprising germanium, antimony, and tellurium. 
   
   
       16 . The method of  claim 1 , wherein the phase change feature comprises a transition metal oxide. 
   
   
       17 . An integrated circuit comprising one or more memory cells, at least one of the one or more memory cells formed at least in part by:
 forming a dielectric layer;   patterning a hole in the dielectric layer by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material; and   forming a phase change feature on the dielectric layer, a portion of the phase change feature at least partially filling the hole in the dielectric layer;   wherein at least a portion of the patterned dielectric layer remains in the ultimate memory cell.   
   
   
       18 . The integrated circuit of  claim 17 , wherein the integrated circuit comprises random access memory circuitry. 
   
   
       19 . The integrated circuit of  claim 17 , wherein the integrated circuit comprises nonvolatile memory circuitry. 
   
   
       20 . An apparatus comprising an integrated circuit, the integrated circuit comprising one or more memory cells, at least one of the one or more memory cells formed at least in part by:
 forming a dielectric layer;   patterning a hole in the dielectric layer by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material; and   forming a phase change feature on the dielectric layer, a portion of the phase change feature at least partially filling the hole in the dielectric layer;   wherein at least a portion of the patterned dielectric layer remains in the ultimate memory cell.