Threshold Adjustment for High-K Gate Dielectric CMOS

Abstract

A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another.

1 . A CMOS structure, comprising:
 at least one first type FET device, said first type FET comprises:   a first gate insulator comprising a first high-k dielectric;   a first liner composed of oxide and having a first thickness between about 0.2 nm and 1.2 nm;   at least one second type FET device, said second type FET comprises:   a second gate insulator comprising a second high-k dielectric;   a second liner composed of oxide and having a second thickness, said second thickness being at least three times larger than said first thickness; and   wherein said second thickness is sufficiently large for oxygen to be capable of passing through said second liner and reaching said second gate insulator, while said first thickness is capable of substantially blocking oxygen from reaching said first gate insulator through said first liner, whereby oxygen exposure is capable to shift the threshold of said first type FET, while leaving substantially unchanged the threshold of said second type FET.   
   
   
       2 . The CMOS structure of  claim 1 , wherein said first type FET device is a PFET device, and said second type FET device is an NFET device. 
   
   
       3 . The CMOS structure of  claim 1 , wherein said first type FET device is an NFET device, and said second type FET device is a PFET device. 
   
   
       4 . The CMOS structure of  claim 1 , wherein said first high-k dielectric and said second high-k dielectric are of a same material. 
   
   
       5 . The CMOS structure of  claim 1 , wherein said same material is HfO 2 . 
   
   
       6 . The CMOS structure of  claim 1 , wherein said first type FET device comprises a first gate, wherein said first gate comprises a first metal. 
   
   
       7 . The CMOS structure of  claim 6 , wherein said first metal is in direct contact with said first gate insulator. 
   
   
       8 . The CMOS structure of  claim 6 , wherein a cap layer is sandwiched inbetween said first metal and said first gate insulator. 
   
   
       9 . The CMOS structure of  claim 1 , wherein said second type FET device comprises a second gate, wherein said second gate comprises a second metal, wherein said second metal is in direct contact with said second gate insulator. 
   
   
       10 . A method for processing a CMOS structure, comprising:
 in a first type FET device, implementing a first gate insulator comprising a first high-k dielectric, and fabricating a temporary liner;   in said first type FET device, removing completely said temporary liner by etching;   in said first type FET device, depositing a chemical oxide liner in place of said temporary liner with a first thickness of between about 0.2 nm and 1.2 nm;   in a second type FET device, implementing a second gate insulator comprising a second high-k dielectric, and fabricating a second liner consisting essentially of oxide and having a second thickness, wherein said second thickness is selected to be at least three times larger than said first thickness; and   exposing said first type FET device and said second type FET device to oxygen, wherein oxygen penetrates through said second liner reaching said second high-k dielectric of said second gate insulator, and causing a predetermined shift in the threshold voltage of said second type FET device, while due to said first thickness oxygen is essentially prevented from penetrating to said first high-k dielectric of said first gate insulator, whereby the threshold voltage of said first type FET device stays unchanged.   
   
   
       11 . The method of  claim 10 , wherein said first type FET device is selected to be a PFET device, and said second type FET device is selected to be an NFET device. 
   
   
       12 . The method of  claim 10 , wherein said first type FET device is selected to be an NFET device, and said second type FET device is selected to be a PFET device. 
   
   
       13 . The method of  claim 10 , wherein said first high-k dielectric and said second high-k dielectric are selected to be of a same material. 
   
   
       14 . The method of  claim 13 , wherein said same material is selected to be HfO 2 . 
   
   
       15 . The method of  claim 10 , further comprising:
 depositing a single layer of oxide over said first type FET device and said second type FET device, and fabricating said temporary liner and said second liner from said single layer of oxide.   
   
   
       16 . The method of  claim 10 , further comprising:
 in said first type FET device, implementing a first gate comprising a first metal;   in a second type FET device, implementing a second gate comprising a second metal.   
   
   
       17 . The method of  claim 16 , wherein for said first gate, processing a cap layer to be sandwiched inbetween said first gate insulator and said first metal. 
   
   
       18 . The method of  claim 16 , wherein for said second gate, processing said second metal in such manner to be in direct contact with said second insulator. 
   
   
       19 . A processor, comprising:
 at least one CMOS circuit, said CMOS further comprising:   at least one first type FET device with a first gate insulator comprising a first high-k dielectric, and with a first liner composed of oxide having a thickness between about 0.2 nm and 1.2 nm; and   at least one second type FET device with a second gate insulator comprising a second high-k dielectric, and with a second liner composed of oxide, wherein said second liner is at least three times thicker than said first liner.   
   
   
       20 . The processor of  claim 19 , wherein said processor has a plurality of said second type FET devices, wherein thresholds of said plurality of second type FET devices have at least two differing values, wherein said differing values are separated by at least 50 mV.