Apparatus and method for selectively recessing spacers on multi-gate devices

Abstract

Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed.

1 - 13 . (canceled) 
   
   
       14 . A multi-gate semiconductor apparatus comprising: 
     a body having a top surface and side surfaces; 
     a gate formed on the top surface of the body; 
     a dielectric spacer formed on side surfaces of the gate; 
     a dielectric cap formed on a top surface of the dielectric spacer and adjacent to the side surfaces of the gate; and 
     an epitaxial layer formed on the top surface of the body and the side surfaces of the body. 
   
   
       15 . The multi-gate semiconductor apparatus of  claim 14 , further including a silicide layer formed on the epitaxial layer. 
   
   
       16 . The multi-gate semiconductor apparatus of  claim 14 , wherein the dielectric spacer is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, and titanium oxide. 
   
   
       17 . The multi-gate semiconductor apparatus of  claim 14 , wherein the gate comprises an oxide or a high-K gate dielectric layer. 
   
   
       18 . The multi-gate semiconductor apparatus of  claim 17 , wherein the high-K gate dielectric layer is selected from the group consisting of lanthanum oxide, tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, lead-zirconate-titanate, barium-strontium-titanate, and aluminum oxide. 
   
   
       19 . The multi-gate semiconductor apparatus of  claim 14 , wherein the body is selected from the group consisting of silicon, gallium-arsenide, and indium antimonide.