SYSTEM FOR ISOLATING A SHORT-CIRCUITED INTEGRATED CIRCUIT (IC) FROM OTHER ICs ON A SEMICONDUCTOR WAFER

Abstract

A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

1 . An electronic circuit comprising:
 an external communications node;   an internal circuit;   control circuitry coupled to the external communications node and configured to sense one of a high current and a short circuit in the internal circuit, the control circuitry comprising:
 a PMOS transistor having a first doped region coupled to the external communications node, a gate, and a second doped region; 
 a first resistance coupled between the external communications node and the gate of the transistor; and 
 a second resistance coupled between the second doped region of the transistor and a reference voltage node; and 
   switching circuitry coupled to the second doped region and the internal circuit, the switching circuitry being configured to selectively isolate the internal circuit from the external communications node in response to receiving a signal from the second doped region.   
   
   
       2 . The electronic circuit of  claim 1 , wherein the control circuitry further comprises:
 a second PMOS transistor having a first doped region coupled to the external communications node, a gate, and a second doped region coupled to the switching circuitry; and   an inverter coupled between the switching circuitry and the gate of the second PMOS transistor.   
   
   
       3 . The electronic circuit of  claim 1 , wherein the external communications node comprises a test node. 
   
   
       4 . The electronic circuit of  claim 3 , wherein the test node comprises a probe pad. 
   
   
       5 . The electronic circuit of  claim 4 , wherein the probe pad comprises a bond pad. 
   
   
       6 . The electronic circuit of  claim 1 , wherein the first doped region comprise a source and the second doped region comprises a drain. 
   
   
       7 . The electronic circuit of  claim 1 , wherein the first and second resistances comprise first and second resistive devices. 
   
   
       8 . The electronic circuit of  claim 1 , wherein the reference voltage node is coupled to a supply voltage. 
   
   
       9 . The electronic circuit of  claim 8 , wherein the supply voltage comprises a ground voltage. 
   
   
       10 . The electronic circuit of  claim 5 , wherein the bond pad is configured to receive a supply voltage. 
   
   
       11 . The electronic circuit of  claim 5 , wherein the bond pad is configured to receive a test voltage. 
   
   
       12 . The electronic circuit of  claim 1 , wherein the internal circuit is coupled to the reference voltage node. 
   
   
       13 . The electronic circuit of  claim 1 , wherein the control circuitry is coupled between the switching circuitry and the external communications node. 
   
   
       14 . The electronic circuit of  claim 1 , wherein the first doped region of the transistor and the first resistance are directly connected to the external communications node. 
   
   
       15 . A system comprising:
 control circuitry within an integrated circuit for sensing one of a high current and a short in an internal circuit of the integrated circuit; and   circuitry for isolating the internal circuit from circuitry external to the integrated circuit in response to the control circuitry sensing one of a high current and a short.   
   
   
       16 . The system of  claim 15 , wherein the circuitry for isolation the internal circuit from circuitry external to the integrated circuit comprises one of a bipolar junction transistor and a micro-relay. 
   
   
       17 . The system of  claim 15 , further comprising:
 isolating the internal circuit from another integrated circuit on a wafer.   
   
   
       18 . The system of  claim 15 , further comprising:
 isolating the internal circuit from a pad.   
   
   
       19 . The system of  claim 18 , wherein the pad comprises a bond pad. 
   
   
       20 . The system of  claim 18 , wherein the pad comprises a probe pad. 
   
   
       21 . The system of  claim 15 , further comprising:
 switching circuitry on the integrated circuit.   
   
   
       22 . The system of  claim 15 , further comprising:
 switching circuitry located on a probe card.   
   
   
       23 . The system of  claim 15 , wherein the circuitry for isolating the internal circuit from circuitry external to the integrated circuit automatically isolates the internal circuit. 
   
   
       24 . A system comprising:
 control circuitry for sensing one of a high current and a short in an internal circuit of an integrated circuit; and   switching circuitry for automatically isolating the internal circuit from circuitry external to the integrated circuit in response to the control circuitry sensing one of a high current and a short.   
   
   
       25 . The system of  claim 24 , wherein the control circuitry comprises control circuitry within the integrated circuit. 
   
   
       26 . The system of  claim 24 , wherein the switching circuitry automatically isolates the internal circuit when sensing a short to ground. 
   
   
       27 . The system of  claim 24 , wherein the switching circuitry automatically isolates the internal circuit when sensing excessive current. 
   
   
       28 . The system of  claim 24 , wherein the switching circuitry automatically isolates the internal circuit when sensing high voltage. 
   
   
       29 . The system of  claim 24 , wherein the switching circuitry automatically isolates the internal circuit when sensing low voltage. 
   
   
       30 . The system of  claim 24 , wherein the switching circuitry automatically isolates the internal circuit when the applied voltage is no longer applied. 
   
   
       31 . A system comprising:
 control circuitry for sensing a short in an internal circuit of the integrated circuit;   a bipolar junction transistor for isolating the internal circuit from circuitry external to the integrated circuit in response to the control circuitry sensing one of a high current and a short.   
   
   
       32 . A system comprising:
 control circuitry for sensing a short in an internal circuit of the integrated circuit; and   a micro-relay for isolating the internal circuit from circuitry external to the integrated circuit in response to the control circuitry sensing one of a high current and a short.   
   
   
       33 . The system of  claim 32 , wherein the control circuitry comprises circuitry for sensing current drawn by the internal circuit that exceeds a predetermined threshold and for outputting the control signal in response thereto. 
   
   
       34 . The electronic system of  claim 33 , wherein the control circuitry comprises circuitry for sensing a voltage applied to the internal circuit that is below a predetermined threshold and for outputting the control signal in response thereto. 
   
   
       35 . A method for testing a plurality of integrated circuits of a semiconductor die of a plurality of semiconductor die of a wafer comprising:
 sensing one of a high current level and a short in a first internal circuit of the plurality of integrated circuits of a first semiconductor die of the plurality of semiconductor die using control circuitry; and   automatically isolating the first internal circuit of the first semiconductor die from circuitry external to the integrated circuit in response to the control circuitry sensing a one of a high current level and a short in the first internal circuit of the plurality of integrated circuits using circuitry for automatically isolating the first internal circuit of the first semiconductor die from circuitry external to the integrated circuit.   
   
   
       36 . The method of  claim 35 , further comprising:
 sensing another internal circuit of the plurality of integrated circuits of a first semiconductor die of the plurality of circuits of the first semiconductor die of the plurality of semiconductor dice using control circuitry within an integrated circuit for sensing one of a high current level and a short; and   automatically isolating the another internal circuit of the first semiconductor die from circuitry external to the another integrated circuit in response to the control circuitry sensing one of a high current level and a short in the another internal circuit of the plurality of integrated circuits using circuitry for automatically isolating the another internal circuit of the first semiconductor die from circuitry external to the integrated circuit.   
   
   
       37 . The method of  claim 35 , further comprising:
 disconnecting the first internal circuit of the first semiconductor die upon detecting one of one of a high current level and a short in the first internal circuit of the first semiconductor die.   
   
   
       38 . The method of  claim 35 , further comprising:
 sensing one of a high current level and a short for each internal circuit of the plurality of integrated circuits of the first semiconductor die of the plurality of semiconductor die; and   automatically isolating each internal circuit of the first semiconductor die from circuitry external to the integrated circuit in response to the control circuitry sensing one of a high current level and a short in an internal circuit of the plurality of integrated circuits using circuitry for automatically isolating the first internal circuit of the first semiconductor die from circuitry external to the integrated circuit.   
   
   
       39 . The method of  claim 35 , further comprising:
 disconnecting the first semiconductor die from the plurality of semiconductor die having any internal circuit having one of a high current level and a short circuit.   
   
   
       40 . The method of  claim 39 , further comprising:
 connecting the plurality of semiconductor die in parallel;   sensing one of a high current level and a short in a first internal circuit of the plurality of integrated circuits of the plurality of semiconductor die connected in parallel using control circuitry; and   automatically isolating the first internal circuit of the plurality of semiconductor die connected in parallel from circuitry external to the integrated circuit in response to the control circuitry sensing a one of a high current level and a short in the first internal circuit of the plurality of integrated circuits using circuitry for automatically isolating the first internal circuit of the first semiconductor die from circuitry external to the integrated circuit.   
   
   
       41 . The method of  claim 40 , further comprising:
 sensing another internal circuit of the plurality of integrated circuits of the plurality of semiconductor die connected in parallel of the plurality of circuits of the first semiconductor die of the plurality of semiconductor dice using control circuitry within an integrated circuit for sensing one of a high current level and a short; and   automatically isolating the another internal circuit of the plurality of semiconductor die connected in parallel from circuitry external to the another integrated circuit in response to the control circuitry sensing one of a high current level and a short in the another internal circuit of the plurality of integrated circuits using circuitry for automatically isolating the another internal circuit of the first semiconductor die from circuitry external to the integrated circuit.