3d integrated circuit system and method

Abstract

A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.

1 . A three dimensional multilayer integrated circuit comprising:
 a first device layer with single crystal fabrication regions; and   a second device layer with single crystal fabrication regions, wherein said single crystal fabrication regions of said second device layer are formed while said second layer is on top of said first layer, with minimal detrimental heat transfer to said first device layer utilizing a controlled laser layer crystallization process for re-crystallization, wherein a crystallization area is defined to prevent undesired heat transfer between sad first device layer and said second device layer and said crystallization area is included in a single crystal fabrication region of said second device layer formed from silicon seed of said first device layer.   
     
     
         2 . A three dimensional multilayer integrated circuit of  claim 1  wherein said single crystal fabrication regions of said second device layer are formed from silicon seed of said first device layer. 
     
     
         3 . A three dimensional multilayer integrated circuit of  claim 1  wherein said single crystal fabrication regions of said second layer are defined by silicon isolation trenches. 
     
     
         4 . A three dimensional multilayer integrated circuit of  claim 1  wherein said single crystal fabrication regions are the size of a transistor. 
     
     
         5 . A three dimensional multilayer integrated circuit of  claim 1  wherein said first layer comprises peripheral devices and said second layer comprises core devices. 
     
     
         6 . A three dimensional multilayer integrated circuit of  claim 1  wherein said first layer and said second layer comprise similar circuitry arrays. 
     
     
         7 . A three dimensional multilayer integrated circuit of  claim 1  wherein said first layer is utilized in association with a first application and said second layer is utilized in association with a second application.