Reducing external resistance of a multi-gate device using spacer processing techniques

Abstract

Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more to multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.

1 - 9 . (canceled) 
     
     
         10 . An apparatus comprising:
 a semiconductor substrate;   at least one multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions;   epi-growth coupled to the source and drain regions of the multi-gate fin;   a gate electrode coupled with the gate region of the multi-gate fin; and   a spacer gate dielectric coupled to the gate electrode wherein substantially no spacer gate dielectric is disposed between the gate electrode and the multi-gate fin in the gate region.   
     
     
         11 . An apparatus according to  claim 10  wherein the multi-gate fin has a top surface, a first sidewall surface, and a second sidewall surface wherein the source and drain regions have epi-growth on the top surface, the first sidewall surface, and the second sidewall surface, the source and drain regions being substantially free of the spacer gate dielectric material on the top surface, the first sidewall surface, and the second sidewall surface. 
     
     
         12 . An apparatus according to  claim 11  wherein the source and drain regions of the multi-gate fin are not coupled directly to the spacer gate dielectric material at any time during a spacer gate dielectric formation process. 
     
     
         13 . An apparatus according to  claim 10  wherein the spacer gate dielectric is conformally grown along a sacrificial dielectric and not conformally grown along the gate electrode. 
     
     
         14 . An apparatus according to  claim 10  wherein the semiconductor substrate comprises silicon, the multi-gate fin comprises silicon, the gate electrode comprises polysilicon, and the spacer gate dielectric comprises a nitride material. 
     
     
         15 . An apparatus according to  claim 10  wherein the multi-gate fin comprises a tri-gate fin of a multi-gate transistor device, the tri-gate fin having a top surface, a first sidewall surface, and a second sidewall surface wherein the epi-growth is coupled to the top surface, the first sidewall surface, and the second sidewall surface in the source and drain regions to reduce external resistance (R ext ) in the multi-gate transistor device.