Semiconductor package having side walls and method for manufacturing the same

Abstract

A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding pads. Re-distribution lines are placed on the first insulation layer pattern and include first re-distribution line parts and second re-distribution line parts. The first re-distribution line parts have an end connected with the bonding pads and correspond to the upper surface of the semiconductor chip and the second re-distribution line parts extend from the first re-distribution line parts beyond the side surfaces of the semiconductor chip. A second insulation layer pattern is formed over the semiconductor chip and exposes portions of the first re-distribution line parts and the second re-distribution line parts.

1 . A method for manufacturing a wafer level semiconductor package, comprising the steps of:
 placing at least two semiconductor chips having bonding pads on a carrier substrate;   forming a first insulation layer pattern on the carrier substrate to cover upper surfaces of the semiconductor chips and side surfaces of the semiconductor chips to expose the bonding pads, wherein the side surfaces of a semiconductor chips are connected with the upper surface of the semiconductor chip;   forming re-distribution lines on the first insulation layer pattern, the re-distribution lines comprising:
 first re-distribution line parts connected to corresponding bonding pads; and 
 second re-distribution line parts extending from the first re-distribution line parts beyond the side surfaces of the semiconductor chips; 
   forming a second insulation layer pattern on predetermined portions of the first insulation layer pattern such that portions of the first re-distribution line parts and the second re-distribution line parts are exposed; and   individualizing the respective semiconductor chips.   
     
     
         2 . The method according to  claim 1 , wherein the step of placing the semiconductor chips comprises the steps of:
 inspecting semiconductor chips formed on a wafer and determining good semiconductor chips and bad semiconductor chips;   individualizing the good and bad semiconductor chips from the wafer; and   placing the good semiconductor chips on the carrier substrate.   
     
     
         3 . The method according to  claim 1 , wherein the step of forming the first insulation layer pattern on the carrier substrate comprises the steps of:
 applying a flowable insulation material on the carrier substrate and so as to form a first insulation layer covering the semiconductor chips;   baking the first insulation layer; and   patterning the first insulation layer to define openings for exposing the bonding pads and to expose a portion of the carrier substrate between adjacent semiconductor chips.   
     
     
         4 . The method according to  claim 1 , wherein the step of forming the first insulation layer pattern on the carrier substrate comprises the steps of:
 applying a flowable insulation material on the carrier substrate and so as to form a first insulation layer covering the semiconductor chips;   baking the first insulation layer; and   patterning the first insulation layer to define openings for exposing the bonding pads.   
     
     
         5 . The method according to  claim 1 , further comprising the step of:
 placing connection members on the exposed portions of the first re-distribution line parts and the second re-distribution line parts.   
     
     
         6 . The method according to  claim 1 , wherein, before the step of individualizing the semiconductor chips, the method further comprises the step of:
 separating the carrier substrate from the semiconductor chips.   
     
     
         7 . A method for manufacturing a semiconductor package, comprising the steps of:
 forming partition walls on a bottom plate in a lattice pattern so as to define receiving spaces;   placing good semiconductor chips having bonding pads, in the respective receiving spaces;   forming re-distribution lines having first ends which are electrically connected with the bonding pads and second ends which face away from the first ends and extend over the partition walls; and   cutting the partition walls and the bottom plate to individualize the semiconductor chips.   
     
     
         8 . The method according to  claim 7 , wherein, after the step of forming the re-distribution lines, the method further comprises the step of:
 to forming a solder resist pattern to cover the partition walls and the semiconductor chips, the solder resist pattern having openings for exposing portions of the re-distribution lines.   
     
     
         9 . The method according to  claim 7 , wherein, before the step of forming the partition walls, the method further comprises the step of:
 defining through-holes in partition wall forming regions on the bottom plate by a pressing process.   
     
     
         10 . The method according to  claim 7 , wherein the bottom plate is made of any one of a metal and synthetic resin and the partition walls are made of any one of a metal and a synthetic resin. 
     
     
         11 . The method according to  claim 7 , wherein, before the step of forming the re-distribution lines, the method further comprises the steps of:
 applying an insulation material on the semiconductor chips so as to form an insulation layer for covering the semiconductor chips; and   patterning the insulation layer to expose the bonding pads.   
     
     
         12 . The method according to  claim 7 , wherein, in the step of placing the semiconductor chips in the respective receiving spaces defined by the partition walls, two or more semiconductor chips are arranged on the bottom plate in each respective receiving space in the form of a matrix. 
     
     
         13 . The method according to  claim 7 , wherein, in the step of placing the semiconductor chips in the respective receiving spaces defined by the partition walls, two or more semiconductor chips are sequentially stacked on the bottom plate in each respective receiving space and the two or more semiconductor chips are electrically connected with each other by through-electrodes. 
     
     
         14 . The method according to  claim 7 , wherein, in the step of placing the semiconductor chips in the respective receiving spaces defined by the partition walls, a semiconductor chip module including a plurality of stacked semiconductor chips, which are electrically connected with one another by through-electrodes, is placed in each respective receiving space.