Wafer level diode package structure

Abstract

A wafer level vertical diode package structure includes a first semiconductor layer, a second semiconductor layer, an insulative unit, a first conductive structure, and a second conductive structure. The second semiconductor layer is connected with one surface of the first semiconductor layer. The insulative unit is disposed around a lateral side of the first semiconductor layer and a lateral side of the second semiconductor layer. The first conductive structure is formed on a top surface of the first semiconductor layer and on one lateral side of the insulative layer. The second conductive structure is formed on a top surface of the second semiconductor layer and on another opposite lateral side of the insulative layer.

1 . A wafer level diode package structure, comprising:
 a first semiconductor layer having a peripheral cutting area formed on a peripheral surface thereof;   a second semiconductor layer connected with the first semiconductor layer, wherein the second semiconductor layer has a peripheral cutting area formed on a peripheral surface thereof and substantially flush with the peripheral cutting area of the first semiconductor layer;   an insulative unit disposed around and on the two peripheral cutting areas of the first and the second semiconductor layers, wherein the insulative unit has a peripheral cutting area formed on a peripheral surface thereof;   a first conductive structure formed on a bottom surface of the first semiconductor layer and a bottom surface of the insulative unit, wherein the first conductive structure has a peripheral cutting area formed on a peripheral surface thereof and substantially flush with the peripheral cutting area of the insulative unit; and   a second conductive structure formed on a top surface of the second semiconductor layer and a top surface of the insulative unit, wherein the second conductive structure has a peripheral cutting area formed on a peripheral surface thereof and substantially flush with the peripheral cutting area of the insulative unit.   
     
     
         2 . The wafer level diode package structure as claimed in  claim 1 , wherein the first semiconductor layer is a P-type semiconductor layer, and the second semiconductor layer is an N-type semiconductor layer. 
     
     
         3 . The wafer level diode package structure as claimed in  claim 1 , wherein the first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer. 
     
     
         4 . The wafer level diode package structure as claimed in  claim 1 , wherein the insulative unit is composed of a first insulative layer and a second insulative layer, the first insulative layer is disposed around and on the peripheral cutting area of the first semiconductor layer and one part of the peripheral cutting area of the second semiconductor layer, and the second insulative layer is disposed around and on the other part of the peripheral cutting area of the second semiconductor layer. 
     
     
         5 . The wafer level diode package structure as claimed in  claim 4 , wherein the first insulative layer has a top surface connected to a bottom surface of the second insulative layer. 
     
     
         6 . The wafer level diode package structure as claimed in  claim 1 , wherein the first conductive structure has a first UBM layer formed on the bottom surface of the first semiconductor layer and the bottom surface of the insulative unit, a first conductive layer formed on the first UBM layer, and a second conductive layer formed on the first conductive layer; wherein the second conductive structure has a second UBM layer formed on the top surface of the second semiconductor layer and the top surface of the insulative unit, a first conductive layer formed on the second UBM layer, and a second conductive layer formed on the first conductive layer. 
     
     
         7 . The wafer level diode package structure as claimed in  claim 1 , wherein the first conductive structure and the second conductive structure are vertically and electrically disposed on a PCB by at least two solder balls or at least two layers of solder glue. 
     
     
         8 . The wafer level diode package structure as claimed in  claim 1 , wherein the first semiconductor layer has at least two conductive pads insulated from each other, and the first conductive structure has two conductive structures respectively and electrically connected to the two conductive pads and an insulative structure disposed between the two conductive structures of the first conductive structure.