Method of manufacturing a semiconductor chip package

Abstract

Provided are methods of manufacturing a semiconductor chip package. The method includes forming a plurality of semiconductor chips, each of which includes a semiconductor substrate having a front and back surfaces facing each other, a chip pad provided on the front surface of the semiconductor substrate, and an interconnection pattern extending from the chip pad along a sidewall of the semiconductor substrate, stacking the semiconductor chips such that the interconnection patterns of the semiconductor chips directly contact each other, and reflowing the interconnection patterns of the semiconductor chips to connect the stacked semiconductor chips with each other.

1 . A method of manufacturing a semiconductor chip package, comprising:
 forming a plurality of semiconductor chips, each of the semiconductor chips comprising,
 a semiconductor substrate having a front surface and a back surface, 
 a chip pad on the front surface of the semiconductor substrate, and 
 an interconnection pattern extending from the chip pad along a sidewall of the semiconductor substrate; 
   stacking the semiconductor chips such that the interconnection patterns of the semiconductor chips directly contact each other; and   reflowing the interconnection patterns of the semiconductor chips.   
     
     
         2 . The method of  claim 1 , wherein the interconnection pattern comprises a first connection portion contacting a top surface of the chip pad and a sidewall portion extending from the first connection portion along the sidewall of the semiconductor substrate. 
     
     
         3 . The method of  claim 2 , wherein the interconnection pattern further comprises a second connection portion extending from the sidewall portion outwardly of the semiconductor substrate. 
     
     
         4 . The method of  claim 3 , wherein the first connection portion, the sidewall portion, and the second connection portion have a uniform thickness. 
     
     
         5 . The method of  claim 3 , wherein the stacking of the semiconductor chips is performed such that a first connection portion of a first interconnection pattern overlaps a second connection portion of a second interconnection pattern, wherein the second interconnection pattern is adjacently disposed on the first interconnection pattern. 
     
     
         6 . The method of  claim 3 , wherein the stacking of the semiconductor chips is performed such that a sidewall of a first connection portion of a first interconnection pattern contacts a sidewall of a second connection portion of a second interconnection pattern, wherein the second interconnection pattern is adjacently disposed on the first interconnection pattern. 
     
     
         7 . The method of  claim 1 , wherein the interconnection pattern is formed of a solder material or a metallic material. 
     
     
         8 . The method of  claim 1 , further comprises:
 preparing a wafer including chip regions and a scribe line region between the chip regions, wherein each of the chip regions includes the chip pad connected to semiconductor integrated circuits;   forming a trench in the scribe line region of the wafer;   forming the interconnection pattern extending an inner wall of the trench to a top surface of the chip pad; and   separating the chip regions of the wafer from each other.   
     
     
         9 . The method of  claim 8 , further comprises:
 forming a mask pattern on the wafer, the mask pattern having an opening on the chip pad and on the trench; and   forming a conductive layer in the opening of the mask pattern.   
     
     
         10 . The method of  claim 8 , wherein the wafer comprises a front surface provided with the chip pad and a back surface, and wherein the method further comprises,
 grinding the back surface of the wafer and exposing the interconnection pattern.   
     
     
         11 . The method of  claim 8 , further comprising sawing the wafer along the scribe line region. 
     
     
         12 . The method of  claim 8 , further comprising forming an adhesion pattern on the front surface of the semiconductor substrate and exposing the chip pad. 
     
     
         13 . The method of  claim 12 , wherein forming the adhesion pattern on the back surface of the semiconductor substrate is performed before or after the separating of the chip regions from each other. 
     
     
         14 . The method of  claim 1 , wherein the stacking of the semiconductor chips is performed such that the semiconductor chips are stacked to form a terraced structure. 
     
     
         15 . The method of  claim 1 , wherein the stacking of the semiconductor chips is performed such that even-numbered semiconductor chips of the semiconductor chips arc stacked in an inverted structure, and odd-numbered semiconductor chips of the semiconductor chips are stacked with back surfaces of the odd-numbered semiconductor chips facing downward. 
     
     
         16 .- 19 . (canceled)