Thin semiconductor-on-insulator mosfet with co-integrated silicon, silicon germanium and silicon doped with carbon channels

Abstract

A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.

1 . A method of forming a semiconductor structure comprising:
 etching a silicon layer of a semiconductor on insulator substrate to provide at least a first device region, a second device region and a third device region;   forming a first block mask on the first device region;   forming a silicon germanium layer on at least a portion of the silicon layer in at least one of the second device region and the third device region;   diffusing germanium from the silicon germanium layer into the silicon layer in at least one of the second device region and the third device region;   forming a second block mask over one of the second device region and the third device region in which the germanium from the silicon germanium layer has diffused into the silicon layer; and   forming a silicon doped with carbon layer on an exposed silicon germanium layer that is not covered with the second block mask.   
     
     
         2 . The method of  claim 1 , wherein the silicon layer is planarized or etched to a thickness of less than 10 nm. 
     
     
         3 . The method of  claim 1 , wherein the etching of the silicon layer comprises removing a portion of the silicon layer separating the first device region, the second device region and the third device region. 
     
     
         4 . The method of  claim 1 , wherein the forming of the first block mask over the first device region comprises:
 depositing a first dielectric layer over the first device region, the second device region and the third device region;   forming an first etch mask over the first dielectric layer protecting the portion of the first dielectric layer that is overlying the first device region; and   etching the first dielectric layer selectively to at least the first etch mask and the silicon layer in the second device region and the third device region.   
     
     
         5 . The method of  claim 1 , wherein the forming of the silicon germanium layer comprises epitaxial deposition of silicon germanium from a precursor selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof. 
     
     
         6 . The method of  claim 1 , wherein the diffusing of the germanium from the silicon germanium layer into the silicon layer comprise annealing. 
     
     
         7 . The method of  claim 6 , wherein the annealing comprises a temperature ranging from 800° C. to 1200° C., and a time period ranging from 1 second to 1 hour. 
     
     
         8 . The method of  claim 7 , wherein the diffusing of the germanium from the silicon germanium layer into the silicon layer converts the silicon germanium layer and the silicon layer into a single material layer of silicon germanium comprising a germanium content ranging from 5 wt. % to 60 wt. %. 
     
     
         9 . The method of  claim 1 , wherein the forming of the second block mask comprises:
 depositing a second dielectric layer over the first device region, and the second device region and the third device region;   forming a second etch mask over the second dielectric layer protecting the portion of the second dielectric layer that is overlying the one of the second device region and the third device region; and   etching the second dielectric layer selectively to at least the second etch mask.   
     
     
         10 . The method of  claim 1 , wherein the forming of the silicon doped with carbon layer comprises epitaxial deposition of a silicon material from a precursor selected from the group consisting of silane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), tetrasilane (Si 4 H 10 ), hexachlorodisilane (Si 2 Cl 6 ), tetrachlorosilane (SiCl 4 ), dichlorosilane (Cl 2 SiH 2 ), trichlorosilane (Cl 3 SiH), methylsilane ((CH 3 )SiH 3 ), dimethylsilane ((CH 3 ) 2 SiH 2 ), ethylsilane ((CH 3 CH 2 )SiH 3 ), methyldisilane ((CH 3 )Si 2 H 5 ), dimethyldisilane ((CH 3 ) 2 Si 2 H 4 ), hexamethyldisilane ((CH 3 ) 6 Si 2 ) and combinations thereof, wherein carbon is introduced to the silicon material by ion implantation or in-situ doping during the epitaxial deposition. 
     
     
         11 . The method of  claim 1 , wherein the silicon doped with carbon layer comprises a carbon content ranging from 0.2 wt. % to 2 wt. %. 
     
     
         12 . The method of  claim 1  further comprises removing the silicon germanium layer that is underlying the silicon doped with carbon layer to provide an undercut region between the silicon doped with carbon layer and the buried dielectric layer. 
     
     
         13 . The method of  claim 12 , wherein the removing of the silicon germanium layer comprises an isotropic dry etch composed of hydrochloric acid (HCl). 
     
     
         14 . The method of  claim 12  further comprising filling the undercut region with a dielectric fill material. 
     
     
         15 . The method of  claim 12  further comprising:
 forming at least one low power semiconductor device on the silicon layer within the first device region; 
 forming a p-type semiconductor device on the silicon germanium layer of the second device region; and 
 forming an n-type semiconductor device on the silicon doped with carbon layer of the third device region. 
 
     
     
         16 . A method of fabricating a semiconductor device comprising:
 providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer;   forming at least one low power semiconductor device including a first n-type semiconductor device and a first p-type semiconductor device on the silicon layer within the first device region of the semiconductor substrate;   forming at least one second p-type semiconductor device on the silicon germanium layer of the second device region of the semiconductor substrate, wherein the at least one second p-type semiconductor device has a threshold voltage that is 0.05 V to 0.5 V less than a threshold voltage of the first p-type semiconductor device of the at least one low power semiconductor device; and   forming at least one second n-type semiconductor device on the silicon doped with carbon layer of the third device region of the semiconductor substrate, wherein the at least one second n-type semiconductor device has a threshold voltage that is 0.05 V to 0.3 V less than a threshold voltage of the first n-type semiconductor device of the at least one low power semiconductor device.   
     
     
         17 - 21 . (canceled)