Strained Structure of a Semiconductor Device

Abstract

A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate comprising a major surface;   a p-type Field Effect Transistor (pFET) comprising:   a P-gate stack over the major surface,   a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and   a P-silicide region on the P-strained region; and   an n-type Field Effect Transistor (nFET) comprising:   an N-gate stack over the major surface,   an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and   a N-silicide region on the N-strained region.   
     
     
         2 . The semiconductor device of  claim 1 , wherein a distance between the first top surface and the major surface is in the range of about 5 to 15 nm. 
     
     
         3 . The semiconductor device of  claim 1 , wherein a maximum thickness of the P-silicide region is in the range of about 10 to 25 nm. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the P-silicide region comprises titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, or palladium silicide. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the P-strained region comprises SiGe or SiGe:B. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the P-gate stack comprises a P-work-function metal. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the P-work-function metal comprises TiN, WN, TaN, and Ru. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the P-gate stack comprises a gate dielectric, wherein the gate dielectric the gate dielectric comprises silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectric. 
     
     
         9 . The semiconductor device of  claim 1 , wherein a distance between the second top surface and the major surface is in the range of about 10 to 25 nm. 
     
     
         10 . The semiconductor device of  claim 1 , wherein a maximum thickness of the N-silicide region is in the range of about 10 to 25 nm. 
     
     
         11 . The semiconductor device of  claim 1 , wherein the N-silicide region comprises titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, or palladium silicide. 
     
     
         12 . The semiconductor device of  claim 1 , wherein the N-strained region comprises SiCP or SiP. 
     
     
         13 . The semiconductor device of  claim 1 , wherein the N-gate stack comprises an N-work-function metal. 
     
     
         14 . The semiconductor device of  claim 13 , wherein the N-work-function metal comprises Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr. 
     
     
         15 . The semiconductor device of  claim 1 , wherein the N-gate stack comprises a gate dielectric, wherein the gate dielectric the gate dielectric comprises silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectric. 
     
     
         16 . A method for fabricating a semiconductor device, comprising:
 providing a substrate comprising a major surface;   forming a cavity below the major surface;   epi-growing a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate;   forming a first metal layer over the strained material;   heating the first metal layer and the strained material to form a first silicide region;   forming an interlayer dielectric (ILD) layer over the first silicide region and extending over the substrate;   forming an opening in the ILD layer, wherein the opening is on the first silicide region;   forming a second metal layer on the first silicide region in the opening; and   heating the second metal layer and the strained material to form a second silicide region lower than the first silicide region.   
     
     
         17 . The method of  claim 16 , wherein the step of heating the first metal layer and the strained material comprises
 heating the substrate at a temperature of about 230 to 260° C.;   removing remaining first metal layer; and   heating the substrate at a temperature of about 650 to 750° C.   
     
     
         18 . The method of  claim 16 , wherein the step of heating the second metal layer and the strained material comprises:
 heating the substrate at a temperature of about 230 to 260° C.;   removing remaining second metal layer; and   heating the substrate at a temperature of about 650 to 750° C.   
     
     
         19 . The method of  claim 16 , wherein the step of forming a first metal layer over the strained material is performed by a physical vapor deposition process. 
     
     
         20 . The method of  claim 16 , wherein the cavity is adjacent to one side of a gate stack.