FinFETs with Nitride Liners and Methods of Forming the Same

Abstract

An integrated circuit structure includes a semiconductor substrate, which includes a semiconductor strip. A Shallow Trench Isolation (STI) region is on a side of the semiconductor strip. The STI region includes a first portion comprising an oxide and a second portion free from oxide. The second portion separates the first portion from the semiconductor substrate. A semiconductor fin is over and aligned to the semiconductor strip, wherein the semiconductor fin is higher than a top surface of the STI region.

1 . An integrated circuit structure comprising:
 a semiconductor substrate comprising a semiconductor strip;   a Shallow Trench Isolation (STI) region on a side of the semiconductor strip, wherein the STI region comprises:
 a first portion comprising an oxide; and 
 a second portion free from oxide, wherein the second portion separates the first portion from the semiconductor substrate; and 
   a semiconductor fin over and aligned to the semiconductor strip, wherein the semiconductor fin is higher than a top surface of the STI region.   
     
     
         2 . The integrated circuit structure of  claim 1 , wherein the STI region further comprises a third portion covering the first portion, wherein the second portion and the third portion enclose the first portion therein, and wherein the third portion is free from oxide. 
     
     
         3 . The integrated circuit structure of  claim 2 , wherein the second portion of the STI contacts a sidewall of the first portion and a sidewall of the third portion. 
     
     
         4 . The integrated circuit structure of  claim 1 , wherein the first portion comprises silicon oxide, and wherein the second portion comprises silicon nitride. 
     
     
         5 . The integrated circuit structure of  claim 1 , wherein the second portion of the STI region comprises a sidewall portion in physical contact with a sidewall of the semiconductor strip, and a bottom portion underlying the first portion and in contact with a top surface of the semiconductor substrate. 
     
     
         6 . The integrated circuit structure of  claim 1  further comprising a re-growth semiconductor region over the semiconductor strip, with the semiconductor fin being a portion of the re-growth semiconductor region, wherein an interface between the semiconductor strip and the re-growth semiconductor region is lower than a top surface of the STI region. 
     
     
         7 . The integrated circuit structure of  claim 1 , wherein the second portion of the STI region forms a conformal layer, with horizontal portions and vertical portions of the second portion having substantially a same thickness. 
     
     
         8 . The integrated circuit structure of  claim 1  further comprising:
 a gate dielectric on a top surface and sidewalls of the semiconductor fin; and 
 a gate electrode over the gate dielectric. 
 
     
     
         9 . An integrated circuit structure comprising:
 a semiconductor substrate comprising a semiconductor strip; and   Shallow Trench Isolation (STI) regions on opposite sides of the semiconductor strip, wherein each of the STI regions comprises:
 an oxide region; and 
 a silicon nitride region over and in contact with the oxide region; and 
   a semiconductor fin over and aligned to the semiconductor strip, wherein the semiconductor fin is higher than a top surface of the silicon nitride region.   
     
     
         10 . The integrated circuit structure of  claim 9 , wherein each of the STI regions further comprises a silicon nitride liner comprising:
 a sidewall portion between and in contact with a first sidewall of the semiconductor strip and a sidewall of the oxide region; and   a bottom portion underlying and in contact with the oxide region.   
     
     
         11 . The integrated circuit structure of  claim 10 , wherein a side edge of the silicon nitride region is in contact with a sidewall of the silicon nitride liner. 
     
     
         12 . The integrated circuit structure of  claim 10 , wherein a top surface of the silicon nitride region is substantially level with a top edge of the silicon nitride liner. 
     
     
         13 . The integrated circuit structure of  claim 10 , wherein the silicon nitride liner forms a basin, with the oxide region in the basin, and wherein the silicon nitride region and the silicon nitride liner fully enclose the oxide region. 
     
     
         14 . The integrated circuit structure of  claim 9  further comprising:
 a gate dielectric on a top surface and sidewalls of the semiconductor fin, wherein the gate dielectric is in contact with a top surface of the silicon nitride region; and 
 a gate electrode over the gate dielectric, wherein the gate dielectric, the gate electrode, and the semiconductor fin are comprised in a Fin Field-Effect Transistor (FinFET). 
 
     
     
         15 .- 20 . (canceled) 
     
     
         21 . An integrated circuit structure comprising:
 a semiconductor substrate;   a Shallow Trench Isolation (STI) region extending into the semiconductor substrate, wherein the STI region comprises:
 a first dielectric material; and 
 second dielectric materials fully enclosing the first dielectric material therein, wherein the second dielectric materials are different from the first dielectric material. 
   
     
     
         22 . The integrated circuit structure of  claim 21  further comprising:
 a portion of the semiconductor substrate contacting an edge of the STI region; and 
 a semiconductor fin with an edge aligned to a sidewall of the STI region, wherein the semiconductor fin is higher than a top surface of the portion of the semiconductor substrate. 
 
     
     
         23 . The integrated circuit structure of  claim 21 , wherein all of the second dielectric materials are formed of a same dielectric material. 
     
     
         24 . The integrated circuit structure of  claim 21 , wherein the first dielectric material comprises silicon oxide, and the second dielectric materials comprise silicon nitride. 
     
     
         25 . The integrated circuit structure of  claim 21 , wherein the second dielectric materials comprise a first portion overlapping the first dielectric material, and a second portion comprising:
 sidewall portions encircling and in contact with edges of the first dielectric material and the first portion of the second dielectric materials; and   a bottom portion overlapped by the first dielectric material.   
     
     
         26 . The integrated circuit structure of  claim 25 , wherein the sidewall portions and the bottom portion of the second dielectric materials are connected continuously with no distinguishable interface therebetween, and the first portion and the sidewall portions have distinguishable interfaces.