Wafer dicing with wide kerf by laser scribing and plasma etching hybrid approach

Abstract

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, approaches for wafer dicing with wide kerf by using a laser scribing and plasma etching hybrid approach are described. For example, a method of dicing a semiconductor wafer including a plurality of integrated circuits separated by dicing streets involves forming a mask above the semiconductor wafer, the mask having a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a laser scribing process to provide a patterned mask having a pair of parallel gaps for each dicing street, exposing regions of the semiconductor wafer between the integrated circuits. Each gap of each pair of parallel gaps is separated by a distance. The method also involves etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.

What is claimed is: 
     
         1 . A singulated semiconductor apparatus, comprising:
 a plurality of singulated integrated circuits disposed on a dicing tape; and   one or more portions of a semiconductor wafer disposed on the dicing tape, among the singulated integrated circuits, and corresponding to dicing streets of the semiconductor wafer.   
     
     
         2 . The singulated semiconductor apparatus of  claim 1 , wherein the one or more portions of the semiconductor wafer are portions of a single crystalline silicon semiconductor wafer. 
     
     
         3 . The singulated semiconductor apparatus of  claim 1 , wherein the one or more portions of the semiconductor wafer comprise a residual mask layer thereon. 
     
     
         4 . The singulated semiconductor apparatus of  claim 1 , wherein the one or more portions of the semiconductor wafer comprise one or more metallization layers thereon. 
     
     
         5 . The singulated semiconductor apparatus of  claim 1 , wherein each of the one or more portions of the semiconductor wafer is spaced approximately in the range of 10-15 microns from a nearest of the singulated integrated circuits. 
     
     
         6 . The singulated semiconductor apparatus of  claim 1 , wherein neighboring ones of the singulated integrated circuits are spaced apart by a distance approximately in the range of 50-85 microns. 
     
     
         7 . A singulated semiconductor apparatus, comprising:
 a plurality of singulated integrated circuits disposed on a dicing tape;   one or more portions of a single crystalline silicon wafer disposed on the dicing tape, among the singulated integrated circuits, and corresponding to dicing streets of the single crystalline silicon wafer;   one or more metallization layers disposed above the one or more portions of the single crystalline silicon wafer; and   a residual mask layer disposed above the one or more metallization layers of the one or more portions of the single crystalline silicon wafer.   
     
     
         8 . The singulated semiconductor apparatus of  claim 7 , wherein each of the one or more portions of the semiconductor wafer is spaced approximately in the range of 10-15 microns from a nearest of the singulated integrated circuits. 
     
     
         9 . The singulated semiconductor apparatus of  claim 7 , wherein neighboring ones of the singulated integrated circuits are spaced apart by a distance approximately in the range of 50-85 microns.