Semiconductor structure and method for manufacturing the same

Abstract

The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing an SOI substrate, onto which a heavily doped buried layer and a surface active layer are formed; forming a gate stack and sidewall spacers on the substrate; forming an opening at one side of the gate stack, wherein the opening penetrates through the surface active layer, the heavily doped buried layer and reaches into a silicon film located on an insulating buried layer of the SOI substrate; filling the opening to form a plug; forming source/drain regions, wherein the source region overlaps with the heavily doped buried layer, and a part of the drain region is located in the plug. Accordingly, the present invention further provides a semiconductor structure. In the present invention, the heavily doped buried layer is favorable for reducing width of depletion layers at source/drain regions and suppressing short-channel effects. The heavily doped buried layer overlaps with the source region, which thence forms a heavily doped pn junction favorable for suppressing floating body effects of SOI MOS devices, thereby improving performance of semiconductor devices. Besides, no body contact is needed in the present invention, thus device area and manufacturing cost are saved.

1 . A method for manufacturing a semiconductor structure, comprising:
 (a) providing an SOI substrate, on which a heavily doped buried layer and a surface active layer are formed;   (b) forming a gate stack and sidewall spacers on the substrate;   (c) forming an opening on one side of the gate stack, wherein the opening penetrates through the surface active layer, the heavily doped buried layer and reaches into a silicon film located on an insulating buried layer of the SOI substrate;   (d) filling the opening to form a plug; and   (e) forming source/drain regions, wherein the source region overlaps with the heavily doped buried layer, and a part of the drain region is located in the plug.   
     
     
         2 . The method of  claim 1 , wherein at step (a), the method for forming the heavily doped buried layer is ion implantation or performing in-situ doping epitaxy on the silicon film of the SOI substrate. 
     
     
         3 . The method of  claim 1 , wherein at step (a), the method for forming the surface active layer is performing in-situ doping epitaxy on the heavily doped buried layer. 
     
     
         4 . The method of  claim 1 , wherein at step (a), the materials of the heavily doped buried layer are Si, Ge or SiGe, and the doping concentration is 10 18 -10 20  cm −3 , and the heavily doped buried layer is P-type doped for NMOS and N-type doped for PMOS. 
     
     
         5 . The method of  claim 1 , wherein at step (a), the materials of the surface active layer are Si, Ge or SiGe, and the doping concentration is 10 15 -10 18  cm −3 , and the surface active layer is P-type doped for NMOS and N-type doped for PMOS. 
     
     
         6 . The method of  claim 1 , wherein at step (c), the step for forming the opening comprises:
 (i) forming a mask layer to cover the gate stack and the substrate;   (ii) etching the mask layer to expose a part of the surface active layer on one side of the gate stack; and   (iii) etching to form the opening that penetrates through the surface active layer, the heavily doped buried layer and reaches into the silicon film on the insulating layer of the SOI substrate.   
     
     
         7 . The method of  claim 1 , wherein, at step (d), the method for filling the opening is an epitaxial process. 
     
     
         8 . The method of  claim 1 , wherein step (d) further comprises filling the opening by an epitaxial process so that the opening is higher than the heavily doped buried layer, and then performing in-situ doping epitaxy to form the drain region. 
     
     
         9 . The method of  claim 1 , wherein at step (d), the materials of the plug are Si, Ge or SiGe. 
     
     
         10 . A semiconductor structure comprising an SOI substrate, a heavily doped buried layer, a surface active layer, a gate stack, sidewall spacers, a source region and a drain region, wherein,
 the SOI substrate comprises, from bottom to top, a base layer, an insulating buried layer and a silicon film;   the heavily doped buried layer is located on the silicon film and under the source region and the gate stack;   the surface active layer is located on the heavily doped buried layer;   the gate stack is located on the surface active layer;   the sidewall spacers are located on sidewalls of the gate stack; and   the source region and the drain region, which are embedded into the surface active layer, are located on both sides of the gate stack, and wherein the source region overlaps with the heavily doped buried layer.   
     
     
         11 . The semiconductor structure of  claim 10 , wherein the materials of the heavily doped buried layer are Si, Ge or SiGe, the doping concentration is 10 18 -10 20  cm −3 , and the heavily doped buried layer is P-type doped for NMOS and N-type doped for PMOS. 
     
     
         12 . The semiconductor structure of  claim 10 , wherein the materials of the surface active layer are Si, Ge or SiGe, the doping concentration is 10 15 -10 18  cm −3 , and the surface active layer is P-type doped for NMOS and N-type doped for PMOS. 
     
     
         13 . The semiconductor structure of  claim 10 , wherein a silicon film is provided between the drain region and the insulating buried layer, and the doping concentration of the silicon film is smaller than the doping concentration of the heavily doped buried layer. 
     
     
         14 . The method of  claim 2 , wherein at step (a), the materials of the heavily doped buried layer are Si, Ge or SiGe, and the doping concentration is 10 18 -10 20  cm −3 , and the heavily doped buried layer is P-type doped for NMOS and N-type doped for PMOS. 
     
     
         15 . The method of  claim 3 , wherein at step (a), the materials of the surface active layer are Si, Ge or SiGe, and the doping concentration is 10 15 -10 18  cm −3 , and the surface active layer is P-type doped for NMOS and N-type doped for PMOS.