Carrier mobility in surface-channel transistors, apparatus made therewith, and systems containing same

Abstract

A surface channel transistor is provided in a semiconductive device. The surface channel transistor is either a PMOS or an NMOS device. Epitaxial layers are disposed above the surface channel transistor to cause an increased bandgap phenomenon nearer the surface of the device. A process of forming the surface channel transistor includes grading the epitaxial layers.

What is claimed is: 
     
         1 . A process of forming a semiconductor device stack comprising:
 forming a buffer structure on a semiconductive substrate, wherein the buffer structure includes a nucleation layer a bottom buffer layer above the nucleation layer, and a graded buffer layer;   forming a bottom barrier structure above the buffer structure, wherein the bottom barrier structure includes a bottom barrier layer and a modulation-doped beryllium halo layer above the bottom barrier layer;   forming a quantum-well structure above the bottom barrier structure, wherein the quantum well structure includes a bottom spacer layer, a QW layer, and a top spacer layer; and   forming a top barrier structure above the quantum-well structure, wherein the top barrier structure includes a doping layer and a top barrier layer above the doping layer.   
     
     
         2 . The process of  claim 1 , further including:
 forming an etch-stop layer above the top barrier structure, wherein the etch-stop layer is an InP material;   forming a contact layer above the etch-stop layer; and   forming a gate contact structure in the device stack in a recess that stops on a gate dielectric disposed on the upper spacer.   
     
     
         3 . The process of  claim 1 , wherein forming the modulation doped halo layer results in semiconductive properties the same as in the a doping layer in the top barrier structure. 
     
     
         4 . The process of  claim 1 , wherein the graded buffer layer includes a graded In x Ga 1-x Sb material. 
     
     
         5 . The process of  claim 1 , wherein the graded buffer layer includes a graded In x Ga 1-x As material. 
     
     
         6 . The process of  claim 1 , wherein forming the gradient in the graded buffer layer results in a linear profile gradient. 
     
     
         7 . The process of  claim 1 , wherein forming the gradient in the graded buffer layer results in an exponential profile gradient. 
     
     
         8 . The process of  claim 1 , wherein forming the gradient in the graded buffer layer results in a negative exponential profile gradient. 
     
     
         9 . The process of  claim 1 , wherein forming the gradient in the graded buffer layer results in a gradient including a positive and a negative exponential profile gradient that includes an inflection point. 
     
     
         10 . The process of  claim 9 , wherein the gradient further includes an asymptote. 
     
     
         11 . The process of  claim 1 , wherein forming the gradient in the graded buffer layer results in a gradient including an inflection and a relational concentration where the concentration reverses to a degree to reach the subsequent layer. 
     
     
         12 . The process of  claim 1 , wherein the second epitaxial structure is formed by MBE, CVD, MOCVD, UHCVD, or LPE. 
     
     
         13 . A process of forming a transistor apparatus, comprising:
 forming a first structure of a semiconductive first type, wherein the first structure is a quantum well channel;   forming a second structure above the first structure, wherein the second structure includes a first layer disposed above and on the first structure, and a subsequent layer of a semiconductive second type that is disposed above the first layer;   forming a source/drain region in the first structure;   forming a gate dielectric layer above and on the subsequent layer;   forming a contact layer above and on the subsequent layer; and   forming a metal gate above and on the gate dielectric layer.   
     
     
         14 . The process of  claim 13 , wherein the contact layer is a graded layer. 
     
     
         15 . The process of  claim 13 , wherein the subsequent layer is up to a 30 th  layer after the first layer, and wherein a compositional gradient is formed between the first layer and the subsequent layer. 
     
     
         16 . The process of  claim 15 , wherein the epitaxial second structure is formed by MBE growth, and wherein forming the compositional gradient results in a linear profile gradient. 
     
     
         17 . The process of  claim 15 , wherein the epitaxial second structure is formed by MBE growth, and wherein forming the compositional gradient results in an exponential profile gradient. 
     
     
         18 . The process of  claim 15 , wherein the compositional gradient includes a graded In x Ga 1-x Sb material. 
     
     
         19 . The process of  claim 15 , wherein the compositional gradient includes a graded In x Ga 1-x As material. 
     
     
         20 . The process of  claim 13 , further including:
 forming the first structure above and on a semiconductive substrate, wherein the epitaxial second structure is formed by MBE growth.