US2015147850A1PendingUtilityA1

Methods for processing a semiconductor workpiece

Assignee: INFINEON TECHNOLOGIES AGPriority: Nov 25, 2013Filed: Nov 25, 2013Published: May 28, 2015
Est. expiryNov 25, 2033(~7.3 yrs left)· nominal 20-yr term from priority
H10P 72/7448H10P 72/7422H10P 72/7416H10P 72/743H10P 76/403H10P 72/7402H10P 54/00H10P 52/00H10P 50/695H10P 50/692H10P 50/242H10P 14/44H10P 14/40H10W 20/0698H10P 72/74H01L 21/82H01L 21/283H01L 21/265H01L 2924/37001H01L 2924/151H01L 24/83
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Claims

Abstract

Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method for processing a semiconductor workpiece, the method comprising:
 providing a semiconductor workpiece having one or more kerf regions;   etching the one or more kerf regions from a first side of the workpiece to form one or more trenches in the workpiece;   mounting the workpiece with the first side to a carrier;   thinning the workpiece from a second side of the workpiece so as to open the one or more trenches; and   forming a metallization layer over the second side of the workpiece after thinning the workpiece.   
     
     
         2 . The method of  claim 1 , wherein etching the one or more kerf regions comprises plasma etching the one or more kerf regions. 
     
     
         3 . The method of  claim 1 , further comprising implanting ions into the workpiece from the second side of the workpiece after thinning the workpiece and before forming the metallization layer. 
     
     
         4 . The method of  claim 1 , wherein mounting the workpiece comprises with the first side to the carrier comprises depositing an adhesive over the first side of the workpiece and attaching the workpiece to the carrier by means of the adhesive. 
     
     
         5 . The method of  claim 4 , further comprising applying a foil to the first side of the workpiece before depositing the adhesive. 
     
     
         6 . The method of  claim 5 , wherein the foil is configured to withstand temperatures up to about 100° C. 
     
     
         7 . A method for processing a semiconductor workpiece, the method comprising:
 providing a semiconductor workpiece having one or more kerf regions;   forming a first mask layer over a first side of the workpiece;   patterning the first mask layer to expose the one or more kerf regions;   mounting the workpiece with the patterned first mask layer to a carrier;   forming a second mask layer over a second side of the workpiece;   patterning the second mask layer to expose the one or more kerf regions;   etching the one or more kerf regions from the second side of the workpiece to form one or more trenches in the workpiece extending from the second side to the first side of the workpiece; and   forming a metallization layer over the second side of the workpiece after etching the one or more kerf regions.   
     
     
         8 . The method of  claim 7 , wherein etching the one or more kerf regions from the second side of the workpiece comprises plasma etching the one or more kerf regions from the second side of the workpiece. 
     
     
         9 . The method of  claim 7 , further comprising thinning the workpiece from the second side after mounting the workpiece and before etching the one or more kerf regions. 
     
     
         10 . The method of  claim 7 , wherein at least one of the first and second mask layers comprises a hard mask material. 
     
     
         11 . A method for processing a semiconductor workpiece, the method comprising:
 providing a semiconductor workpiece having one or more kerf regions;   forming a first mask layer over a first side of the workpiece;   patterning the first mask layer to expose the one or more kerf regions;   mounting the workpiece with the patterned first mask layer to a carrier;   forming a second mask layer over a second side of the workpiece;   patterning the second mask layer to expose one or more regions of the workpiece adjacent to the one or more kerf regions;   forming a metallization layer over the patterned second mask layer and the one or more exposed regions of the workpiece adjacent to the one or more kerf regions;   applying a lift-off process to remove the patterned second mask layer and the metallization layer from the one or more kerf regions and form a patterned metallization layer; and   etching the one or more kerf regions from the second side of the workpiece to form one or more trenches in the workpiece extending from the second side to the first side of the workpiece.   
     
     
         12 . The method of  claim 11 , wherein etching the one or more kerf regions from the second side of the workpiece comprises plasma etching the one or more kerf regions from the second side of the workpiece. 
     
     
         13 . The method of  claim 11 , further comprising thinning the workpiece from the second side before forming the second mask layer. 
     
     
         14 . The method of  claim 11 , further comprising forming a protection layer over the patterned metallization layer before etching the one or more kerf regions. 
     
     
         15 . A method for processing a semiconductor workpiece, the method comprising:
 providing a semiconductor workpiece having one or more kerf regions;   forming a mask layer over a first side of the workpiece;   patterning the mask layer to expose the one or more kerf regions;   mounting the workpiece with the patterned mask layer to a carrier;   forming a metallization layer over a second side of the workpiece that is opposite the first side;   patterning the metallization layer to expose the one or more kerf regions; and   etching the one or more kerf regions from the second side of the workpiece to form one or more trenches in the workpiece extending from the second side to the first side of the workpiece.   
     
     
         16 . The method of  claim 15 , wherein etching the one or more kerf regions from the second side of the workpiece comprises plasma etching the one or more kerf regions from the second side of the workpiece. 
     
     
         17 . The method of  claim 15 , further comprising thinning the workpiece from the second side before forming the metallization layer over the second side. 
     
     
         18 . The method of  claim 15 , wherein the mask layer comprises a hard mask material. 
     
     
         19 . A method for processing a semiconductor workpiece, the method comprising:
 providing a semiconductor workpiece having one or more kerf regions;   forming an etch stop layer over a first side of the workpiece;   mounting the workpiece with the etch stop layer attached to a carrier;   etching the one or more kerf regions from a second side of the workpiece to the etch stop layer to form one or more trenches in the workpiece; and   removing one or more sections of the etch stop layer exposed by the one or more trenches, to extend the one or more trenches through to a surface of the etch stop layer facing the carrier.   
     
     
         20 . The method of  claim 19 , wherein etching the one or more kerf regions comprises plasma etching the one or more kerf regions. 
     
     
         21 . The method of  claim 19 , further comprising thinning the workpiece from the second side before etching the one or more kerf regions from the second side. 
     
     
         22 . The method of  claim 19 , further comprising forming a metallization layer over the second side of the workpiece after etching the one or more kerf regions. 
     
     
         23 . The method of  claim 19 , further comprising forming a metallization layer over the second side of the workpiece after removing the one or more sections of the etch stop layer. 
     
     
         24 . A method for processing a semiconductor workpiece, the method comprising:
 providing a semiconductor workpiece having one or more kerf regions;   removing material of the one or more kerf regions from a first side of the workpiece to form one or more trenches in the workpiece;   forming an adhesive structure over the first side of the workpiece, wherein the adhesive structure at most partially fills the one or more trenches;   mounting the workpiece to a carrier using the adhesive structure;   thinning the workpiece from a second side of the workpiece so as to open the one or more trenches; and   forming a metallization layer over the second side of the workpiece after thinning the workpiece.   
     
     
         25 . The method of  claim 24 , wherein removing material of the one or more kerf regions from the first side of the workpiece comprises etching the one or more kerf regions from the first side of the workpiece. 
     
     
         26 . The method of  claim 25 , wherein etching the one or more kerf regions comprises plasma etching the one or more kerf regions. 
     
     
         27 . The method of  claim 24 , wherein removing material of the one or more kerf regions from the first side of the workpiece comprises sawing the one or more kerf regions from the first side of the workpiece. 
     
     
         28 . The method of  claim 24 , wherein the adhesive structure comprises a protective layer disposed over the first side of the workpiece and an adhesive layer disposed over the protective layer. 
     
     
         29 . The method of  claim 28 , wherein the protective layer comprises a foil. 
     
     
         30 . The method of  claim 29 , wherein the foil is configured to withstand temperatures up to about 100° C.

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