Novel compact charge trap multi-time programmable memory

Abstract

A memory device requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: a substrate; a gate stack on the substrate; a source and drain in the substrate at opposite sides, respectively, of the gate stack; a source extension region in the substrate adjacent the source region, wherein no drain extension region is formed on the other side of the gate stack; a tunnel oxide liner on the substrate at each side of the gate stack and on side surfaces of the gate stack; and a charge-trapping (CT) spacer on each tunnel oxide liner.

What is claimed is: 
     
         1 . A device, comprising:
 a substrate;   a gate stack on the substrate;   a source and drain in the substrate at opposite sides, respectively, of the gate stack;   a source extension region in the substrate adjacent the source region, wherein no drain extension region is formed on the other side of the gate stack;   a tunnel oxide liner on the substrate at each side of the gate stack and on side surfaces of the gate stack; and   a charge-trapping (CT) spacer on each tunnel oxide liner.   
     
     
         2 . The device according to  claim 1 , further comprising:
 an interlayer dielectric (ILD) on the substrate surrounding the gate stack and CT spacers;   a first contact, through the ILD over the drain, at least partially abutting to the CT spacer or separated from the CT spacer by a block oxide liner; and   a second contact, through the ILD over the source.   
     
     
         3 . The device according to  claim 2 , further comprising:
 a first block oxide liner on each side of the first contact; and   a second block oxide liner on each side of the second contact.   
     
     
         4 . The device according to  claim 1 , wherein the gate stack comprises:
 a high-k dielectric layer;   a work-function tuning layer on the high-k dielectric layer; and   a metal gate electrode on the work-function tuning layer.   
     
     
         5 . The device according to  claim 4 , wherein each CT spacer is formed as a layer over each portion of the tunnel oxide liner, the device further comprising:
 a spacer over each CT spacer.   
     
     
         6 . The device according to  claim 4 , further comprising:
 the high-k dielectric layer being on side surfaces of the metal gate electrode; and   the work-function tuning layer being titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), lanthanum (La), lanthanum oxide (La 2 O 3 ), or a combination thereof.   
     
     
         7 . The device according to  claim 1 , further comprising:
 the tunnel oxide liners being formed of an oxide using an in-situ steam generation (ISSG) process, a high temperature oxide (HTO), a silicon oxynitride (SiON), multiple layers of oxide nitride oxide (ONO), or a combination thereof.   
     
     
         8 . The device according to  claim 1 , further comprising:
 the CT spacers being formed of nitride, silicon nitride (SiN), silicon oxynitride (SiON), hafnium oxide (HfO 2 ), tantalum nitride (TaN), or a combination thereof.   
     
     
         9 . A device comprising:
 a substrate;   a gate stack formed on the substrate, the gate stack including a replacement metal gate (RMG) electrode;   a source extension region formed in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack;   a tunnel oxide liner formed on side surfaces of the gate stack and on the substrate on each side of the gate stack;   a charge-trapping (CT) spacer formed on each tunnel oxide liner;   a block oxide liner formed on each CT spacer; and   a source formed in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack,   wherein the source extension region and source are formed on the one side of the gate stack and the drain is formed on the other side of the gate stack with no drain extension region being formed.   
     
     
         10 . The device according to  claim 9 , further comprising:
 an interlayer dielectric (ILD) over an upper surface of the substrate surrounding the gate stack and the CT spacers.   
     
     
         11 . The device according to  claim 10 , further comprising:
 a first contact formed through the ILD over the drain, the first contact separated from the CT spacer by the block oxide liner; and   a second contact formed through the ILD over the source.   
     
     
         12 . The device according to  claim 9 , wherein the gate stack comprises:
 a high-k dielectric layer formed between each of the tunnel oxide liners; and   the replacement metal gate (RMG) electrode on the high-k dielectric layer.   
     
     
         13 . The device according to  claim 12 , further comprising:
 a hardmask layer formed on the RMG electrode.   
     
     
         14 . The device according to  claim 13 , further comprising:
 a work-function tuning layer of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), lanthanum (La), lanthanum oxide (La 2 O 3 ), or a combination thereof formed on the high-k dielectric layer.   
     
     
         15 . The device according to  claim 9 , wherein the CT spacer on the drain side of the gate stack is configured to:
 store charges when a low voltage is applied to the second contact and a program voltage is applied to the first contact;   remove the charges when an erase voltage is applied to one of the first and second contacts and a low voltage is applied to the other of the first and second contacts; and   determine a current or gate threshold voltage when a read voltage is detected on the second contact and a low voltage is applied to the first contact.   
     
     
         16 . A device comprising:
 a substrate;   a gate stack formed on the substrate, the gate stack comprising:
 a high-k dielectric layer, 
 a replacement metal gate (RMG) electrode formed over the high-k dielectric layer, and 
 a hardmask layer formed on the RMG electrode; 
   a source extension region formed in the substrate on one side of the gate stack, wherein a drain extension region is not formed on the other side of the dummy gate stack;   a tunnel liner of oxide formed on each side surface of the gate stack and on the substrate at each side of the gate stack;   a charge-trapping (CT) spacer of nitride, silicon nitride (SiN), silicon oxynitride (SiON), hafnium oxide (HfO 2 ), tantalum nitride (TaN), or a combination thereof on each tunnel liner;   a source formed in the substrate on the one side of the gate stack adjacent the source extension region, and a drain in the substrate on the other side of the gate stack;   an interlayer dielectric (ILD) formed on the substrate surrounding the gate stack and CT spacers;   a first contact formed over the drain at least partially abutting the CT spacer or separated from the CT spacer by a block oxide liner; and   a second contact formed over the source.   
     
     
         17 . The device of  claim 16 , wherein the first and second contacts comprise Al, W, Ta, Ti, TaN, TiN, or a combination thereof. 
     
     
         18 . The device according to  claim 16 , further comprising:
 a work-function tuning layer of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), lanthanum (La), lanthanum oxide (La 2 O 3 ), or a combination thereof formed on the high-k dielectric layer.   
     
     
         19 . The device according to  claim 16 , wherein the source extension region and source are formed on the one side of the gate stack and the drain is formed on the other side of the gate stack with no drain extension region being formed. 
     
     
         20 . The device according to  claim 16 , wherein the CT spacer on the drain side of the dummy gate stack is configured to:
 store charges when a low voltage is applied to the second contact and a program voltage is applied to the first contact;   remove the charges when an erase voltage is applied to one of the first and second contacts and a low voltage is applied to the other of the first and second contacts; and   determine a current or gate threshold voltage when a read voltage is detected on the second contact and a low voltage is applied to the first contact.