Facilitating chip dicing for metal-metal bonding and hybrid wafer bonding

Abstract

A method of forming a stacked assembly of semiconductor chips can include juxtaposing and metallurgically joining kerf metal elements exposed in kerf regions of a first wafer with corresponding kerf metal elements exposed in kerf regions of a second wafer, and affixing undiced semiconductor chips of the first wafer with corresponding undiced semiconductor chips of the second wafer. The assembled wafers are then cut along the dicing lanes thereof into a plurality of individual assemblies of stacked semiconductor chips, each assembly including an undiced semiconductor chip of the first wafer and an undiced semiconductor chip of the second wafer affixed therewith.

What is claimed is: 
     
         1 . A wafer subassembly for use in forming a plurality of individual assemblies of stacked semiconductor chips, comprising:
 a semiconductor wafer and a plurality of kerf metal elements disposed in kerf regions at the surface of the wafer, the kerf regions disposed in dicing lanes between adjacent undiced semiconductor chips of the wafer, the kerf metal elements being configured for direct metal-to-metal joining with corresponding kerf metal elements of at least one other wafer subassembly to form a stacked wafer assembly.   
     
     
         2 . The wafer subassembly of  claim 1 , wherein the wafer subassembly has a thickness of less than 100 microns between opposite exposed surfaces thereof. 
     
     
         3 . The wafer subassembly of  claim 1 , wherein the kerf metal elements include individual rectangular frame elements, each individual rectangular frame element surrounding an individual undiced semiconductor chip of one of the wafers. 
     
     
         4 . The wafer subassembly of  claim 1 , wherein the kerf metal elements of each wafer include at least one continuous kerf metal element which has a first portion extending in a first direction of a length of a first dicing lane parallel to an edge of a first undiced semiconductor chip and parallel to an edge of a second undiced semiconductor chip, and a second portion extending in the first direction, the second portion crossing a second dicing lane that extends in a second direction between the first undiced semiconductor chip and the second undiced semiconductor chip.