Semiconductor device and method for fabricating the same

Abstract

Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor device comprising:
 a semiconductor substrate with a first semiconductor fin and a second semiconductor fin, the first and second semiconductor fins extending, with respect to a top down view, in a first direction and extending along a same line and defining a first recess between facing ends of the first and second semiconductor fins;   a first insulator pattern formed in the first recess and having a top surface at least as high as a top surface of the first semiconductor fin;   a third semiconductor fin and a fourth semiconductor fin, the third and fourth semiconductor fins extending, with respect to a top down view, in the first direction and extending along a same line and defining a second recess between facing ends of the third and fourth semiconductor fins;   a second insulator pattern formed in the second recess and having a top surface at least as high as a top surface of the third semiconductor fin, wherein, with respect to a cross section of the second insulator pattern taken in a direction perpendicular to the second direction at the second recess, the second insulator pattern includes substantially linear sidewalls extending from a top surface of the second insulator pattern and extending along a majority of the height of the second insulator pattern;   a first gate electrode extending along a first sidewall of the first semiconductor fin, the top surface of the first semiconductor fin and a second sidewall of the first semiconductor fin;   a second gate electrode extending along a first sidewall of the second semiconductor fin, a top surface off the second semiconductor fin and a second sidewall of the second semiconductor fin;   a first dummy gate electrode formed on the top surface of the first insulator pattern at the first recess; and   a second dummy gate electrode and a third dummy gate electrode formed on the second insulator pattern.   
     
     
         22 . The semiconductor device of  claim 21 ,
 wherein the second dummy gate electrode is formed on the third semiconductor fin, and the third dummy gate electrode is formed on the fourth semiconductor fin.   
     
     
         23 . The semiconductor device of  claim 22 ,
 wherein the second dummy gate electrode comprises metal at least a portion of which is located directly above the third semiconductor fin and the third dummy gate electrode comprise metal at least a portion of which is located directly above the fourth semiconductor fin.   
     
     
         24 . The semiconductor device of  claim 23 , wherein the metal of the second dummy gate electrode and the metal off the third dummy gate electrode are located directly above respective sidewalls of the second insulator pattern. 
     
     
         25 . The semiconductor device of  claim 21 , wherein, with respect to the cross section at the first recess, the first dummy gate electrode is the only dummy gate electrode on the first insulator pattern. 
     
     
         26 - 33 . (canceled) 
     
     
         34 . A semiconductor device comprising:
 a semiconductor substrate with a first semiconductor fin and a second semiconductor fin, the first and second semiconductor fins extending, with respect to a top down view, in a first direction and extending along a same line and defining a first recess between facing ends of the first and second semiconductor fins;   a first insulator pattern adjacent a major sidewall of the first semiconductor fin and adjacent a major sidewall of the second semiconductor fin;   a second insulator pattern within the first recess;   a first gate electrode extending along the major sidewall of the first semiconductor fin, a top surface of the first semiconductor fin and a top surface of the first insulator pattern adjacent the major sidewall of the first semiconductor fin;   a second gate electrode extending along the major sidewall of the second semiconductor fin, a top surface of the second semiconductor fin and a top surface of the first insulator pattern adjacent the major sidewall of the second semiconductor fin; and   a first dummy gate electrode formed on the top surface of the second insulator pattern,   wherein the top surface of the second insulator pattern at the first recess is higher than top surfaces of the first insulator pattern adjacent the major sidewall of the first semiconductor fin and adjacent the second semiconductor fin.   
     
     
         35 . The semiconductor device of  claim 34 , wherein, with respect to a cross section of the second insulator pattern taken along the first direction, the remaining insulator has a T-shape.