Semiconductor devices including through-silicon-vias and methods of manufacturing the same and semiconductor packages including the semiconductor devices

Abstract

A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure.

1 . A semiconductor device, comprising:
 a via structure through a substrate, a portion of the via structure exposed above a top surface of the substrate, and the via structure having a top surface of which a central portion is concave and including:
 a via electrode including a conductive pattern and a barrier layer pattern surrounding a sidewall of the conductive pattern; and 
 an insulation layer pattern surrounding a sidewall of the via electrode, 
   wherein a top surface of the conductive pattern is lower than that of the insulation layer pattern and is flat,   a protection layer pattern structure on the top surface of the substrate, the protection layer pattern structure surrounding a sidewall of the portion of the via structure that is exposed and including a photosensitive organic material; and   a pad structure contacting a top surface of the portion of the via structure that is exposed, the pad structure having a flat top surface.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the protection layer pattern structure includes a thermosetting organic polymer. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the thermosetting organic polymer comprises any one selected from the group consisting of polyimide, novolac, polybenzoxazole, benzocyclobutene, silicon polymer, epoxy polymer and acrylate polymer. 
     
     
         4 . The semiconductor device of  claim 2 , wherein a top surface of the protection layer pattern structure has a substantially constant height. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the top surface of the conductive pattern is lower than those of both of the barrier layer pattern and the insulation layer pattern. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the top surface of the barrier layer pattern is substantially coplanar with that of the insulation layer pattern. 
     
     
         7 . The semiconductor device of  claim 5 , wherein upper portions of each of the barrier layer pattern and the insulation layer pattern above the conductive pattern have a width that decreases from a bottom toward a top thereof. 
     
     
         8 . The semiconductor device of  claim 1 , wherein a top surface of the barrier layer pattern is lower than that of the insulation layer pattern. 
     
     
         9 . The semiconductor device of  claim 8 , wherein the top surface of the barrier layer pattern is substantially coplanar with that of the conductive pattern. 
     
     
         10 . The semiconductor device of  claim 1 , wherein the top surface of the conductive pattern is lower than that of the substrate. 
     
     
         11 . The semiconductor device of  claim 1 , wherein the conductive pattern includes a metal, the barrier layer pattern includes a metal nitride, and the insulation layer pattern includes silicon nitride. 
     
     
         12 . The semiconductor device of  claim 1 , wherein the pad structure has a bottom surface of which a central portion is concave, and conforms to a contour of the top surface of the via structure. 
     
     
         13 . The semiconductor device of  claim 1 , wherein the pad structure includes a seed pattern thereon. 
     
     
         14 . The semiconductor device of  claim 13 , wherein the pad includes nickel. 
     
     
         15 . The semiconductor device of  claim 1 , wherein the pad structure contacts the via structure and the protection layer pattern structure. 
     
     
         16 . The semiconductor device of  claim 15 , wherein a bottom surface of the pad structure follows a contour defined by variation in respective heights of the top surface of the via structure and a top surface of the protection layer pattern structure. 
     
     
         17 . The semiconductor device of  claim 1 , wherein the semiconductor device includes a plurality of via structures and a plurality of pad structures, and wherein some conductive patterns in the via structures have respective top surfaces at different heights. 
     
     
         18 . The method of  claim 17 , wherein some pad structures have respective top surfaces at different heights. 
     
     
         19 . A semiconductor device, comprising:
 a via structure through a substrate, a portion of the via structure exposed above a top surface of the substrate, and the via structure having a top surface of which a central portion is concave and including:
 a via electrode including a conductive pattern and a barrier layer pattern surrounding a sidewall of the conductive pattern; and 
 an insulation layer pattern surrounding a sidewall of the via electrode, 
   wherein a top surface of the conductive pattern is lower than that of the insulation layer pattern and is flat,   a protection layer pattern structure on the top surface of the substrate, the protection layer pattern structure surrounding a sidewall of the portion of the via structure that is exposed, and a top surface of a first portion of the protection layer pattern structure proximate to the via structure is higher than a second portion of the protection layer pattern structure remote from the via structure relative to the first portion and   a pad structure contacting the portion of the via structure that is exposed, the pad structure having a flat top surface.   
     
     
         20 . (canceled) 
     
     
         21 . (canceled) 
     
     
         22 . A semiconductor device, comprising:
 a via structure through a substrate, a portion of the via structure exposed above a top surface of the substrate;   a protection layer pattern structure on the top surface of the substrate, the protection layer pattern structure surrounding a sidewall of the portion of the via structure that is exposed and having a top surface higher than that of the via structure; and   a pad structure contacting the portion of the via structure that is exposed and contacting the protection layer pattern structure, the pad structure having a flat top surface.   
     
     
         23 .- 56 . (canceled)