Reduction of underfill filler settling in integrated circuit packages

Abstract

Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.

What is claimed is: 
     
         1 . A method, comprising:
 forming an interconnect structure between a die and an integrated circuit substrate, the interconnect structure being configured to route electrical signals between the die and the integrated circuit substrate;   depositing an underfill material between the die and the integrated circuit substrate to form a package, the underfill material comprising a plurality of filler particles, wherein the underfill material surrounds at least a portion of the interconnect structure; and   reducing an electrostatic charge on one or more of the underfill material and the interconnect structure.   
     
     
         2 . The method of  claim 1 , further comprising:
 curing the underfill material; and   applying a magnetic field to the package during the depositing or the curing of the underfill material, wherein the magnetic field applies a force to the filler particles in a direction generally opposite to a direction of gravitational force.   
     
     
         3 . The method of  claim 1 , further comprising:
 inverting the package to position the integrated circuit substrate above the die relative to a downward direction of gravitational force; and   curing the underfill material while the package is inverted with the integrated circuit substrate above the die.   
     
     
         4 . The method of  claim 2 , further comprising curing the underfill material at a cure temperature in the range of 120° C.-130° C., wherein the underfill material has a gel temperature that is less than or equal to the cure temperature. 
     
     
         5 . The method of  claim 1 , wherein the filler particles are 5 μm or less in diameter.