Controlling the Reflow Behaviour of BPSG Films and Devices Made Thereof

Abstract

A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. A ratio of the flow of the dopant source to the flow of the silicon source is a first ratio. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. The ratio of the flow of the dopant source to the flow of the silicon source is a second ratio lower than the first ratio, and stopping the flow of the silicon source after performing the secondary deposition. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a plurality of trenches disposed in a semiconductor substrate;   a plurality of gates formed within the plurality of trenches, wherein each gate of the plurality of gates has a V-shaped groove formed within, the V-shaped groove having a first sidewall and a second sidewall, wherein the first sidewall intersects with the second sidewall at an acute angle inside the trench;   a common drain region disposed in the semiconductor substrate;   a plurality of source regions disposed in the semiconductor substrate; and   a reflown layer of silicate glass disposed over the sidewalls of V-shaped groove of the plurality of gates, wherein a variation in thickness of the layer of silicate glass at the acute vertices and other regions of the layer of silicate glass over the sidewall of the V-shaped groove is between 0.1% to 10%.   
     
     
         2 . The semiconductor device of  claim 1 , wherein a thickness of the reflown layer of silicate glass at a bottom part of the first and the second sidewalls is higher than a thickness of the reflown layer of silicate glass at a top part of the first and the second sidewalls. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the layer of silicate glass is at least 10 nm. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the layer of silicate glass comprises borophosphosilicate glass (BPSG). 
     
     
         5 . The semiconductor device of  claim 1 , wherein each of the plurality of source regions is disposed between adjacent ones of the plurality of trenches. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the acute angle is less than 60°. 
     
     
         7 . The semiconductor device of  claim 1 , further comprising a source contact disposed at an upper portion of each of the plurality of source regions. 
     
     
         8 . A semiconductor device comprising:
 a plurality of trenches disposed in a semiconductor substrate;   a plurality of gates formed within the plurality of trenches;   a common drain region disposed in the semiconductor substrate;   a plurality of source regions disposed in the semiconductor substrate;   a common source disposed over and coupled to the plurality of source regions; and   a reflown layer of silicate glass disposed over the plurality of gates, wherein a variation in thickness of the layer of silicate glass at a central region of the plurality of gates and other regions of the layer of silicate glass is between 0.1% to 10%, and wherein the plurality of gates are separated from the common source by the reflown layer of silicate glass.   
     
     
         9 . The semiconductor device of  claim 8 , wherein each gate of the plurality of gates has a V-shaped groove formed within, the V-shaped groove having a first sidewall and a second sidewall, wherein the first sidewall intersects with the second sidewall at an acute angle inside the trench. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the acute angle is less than 60°. 
     
     
         11 . The semiconductor device of  claim 8 , wherein a thickness of the reflown layer of silicate glass directly over the central region is higher than a thickness of the reflown layer of silicate glass directly over the gate dielectric layer. 
     
     
         12 . The semiconductor device of  claim 8 , wherein each of the plurality of trenches is lined with a gate dielectric layer, an insulating layer disposed in a lower portion of the trench, and a gate material above the insulating layer.