Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or iii-v channel of semiconductor device

Abstract

A method of forming a semiconductor device that includes forming a metal oxide material on a III-V semiconductor channel region or a germanium containing channel region; and treating the metal oxide material with an oxidation process. The method may further include depositing of a hafnium containing oxide on the metal oxide material after the oxidation process, and forming a gate conductor atop the hafnium containing oxide. The source and drain regions are on present on opposing sides of the gate structure including the metal oxide material, the hafnium containing oxide and the gate conductor.

1 . A semiconductor device comprising:
 a channel region of a substrate comprising a germanium containing material;   a gate structure comprising an interface dielectric material comprising germanium, oxygen and nitrogen that is directly on the substrate, a high-k dielectric layer comprising hafnium, aluminum and oxygen on the interface dielectric material, and a gate conductor present atop the high-k dielectric layer; and   a source region and drain region on opposing sides of the channel region.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the interface dielectric material is aluminum oxide, and a gallium enriched InGaAs layer is present adjacent to the high-k dielectric layer. 
     
     
         3 . The semiconductor device of  claim 2 , wherein a gallium concentration in the InGaAs layer decreases as the distance within the InGaAs layer increases from the high-k dielectric layer. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the source and drain regions are present within the substrate. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the source and drain regions are doped with an n-type dopant selected from the group consisting of antimony, arsenic and phosphorous. 
     
     
         6 . The semiconductor device of  claim 4 , wherein the source and drain regions are doped with a p-type dopant of boron. 
     
     
         7 . The semiconductor device of  claim 1 , wherein interface dielectric material comprises (Si)GeO(N). 
     
     
         8 . The semiconductor device of  claim 1 , wherein germanium containing material is germanium, silicon germanium or a combination thereof. 
     
     
         9 . A semiconductor device comprising:
 a channel region of a substrate comprising a III-V material;   a gate structure comprising an interface dielectric material comprising germanium, oxygen and nitrogen that is directly on the substrate, a high-k dielectric layer comprising hafnium, aluminum and oxygen on the interface dielectric material, and a gate conductor present atop the high-k dielectric layer; and   a source region and drain region on opposing sides of the channel region.   
     
     
         10 . The semiconductor device of  claim 9 , wherein the III-V semiconductor channel region comprises a semiconductor material selected from the group consisting of gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), gallium antimonide (GaSb), indium antimonide (InSb), indium gallium antimonide (InGaSb), and combinations thereof. 
     
     
         11 . The semiconductor device of  claim 9 , wherein the interface dielectric material is aluminum oxide, and a gallium enriched InGaAs layer is present adjacent to the high-k dielectric layer. 
     
     
         12 . The semiconductor device of  claim 11 , wherein a gallium concentration in the InGaAs layer decreases as the distance within the InGaAs layer increases from the high-k dielectric layer. 
     
     
         13 . The semiconductor device of  claim 9 , wherein the source and drain regions are present within the substrate. 
     
     
         14 . The semiconductor device of  claim 13 , wherein the source and drain regions are doped with an n-type dopant selected from the group consisting of antimony, arsenic and phosphorous. 
     
     
         15 . The semiconductor device of  claim 13 , wherein the source and drain regions are doped with a p-type dopant of boron. 
     
     
         16 . The semiconductor device of  claim 9 , wherein interface dielectric material comprises (Si)GeO(N). 
     
     
         17 . A gate material stack comprising:
 a gate structure present on a germanium containing channel or III-V semiconductor channel, the gate structure comprising an interface dielectric material comprising germanium, oxygen and nitrogen that is directly on the substrate, a high-k dielectric layer comprising hafnium, aluminum and oxygen on the interface dielectric material, and a gate conductor present atop the high-k dielectric layer.   
     
     
         18 . The gate material stack of  claim 17 , wherein the interface dielectric material is aluminum oxide, and a gallium enriched InGaAs layer is present adjacent to the high-k dielectric layer. 
     
     
         19 . The gate material stack of  claim 17 , wherein a gallium concentration in the InGaAs layer decreases as the distance within the InGaAs layer increases from the high-k dielectric layer. 
     
     
         20 . The gate material stack of  claim 17 , wherein interface dielectric material comprises (Si)GeO(N).