Controlling the Reflow Behaviour of BPSG Films and Devices Made Thereof

Abstract

A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a plurality of trenches disposed in a semiconductor substrate;   a plurality of gates formed within the plurality of trenches;   a common drain region disposed in the semiconductor substrate;   a plurality of source regions disposed in the semiconductor substrate;   a common source disposed over and coupled to the plurality of source regions; and   a reflown layer of silicate glass disposed over the plurality of gates, wherein a variation in thickness of the layer of silicate glass at a central region of the plurality of gates and other regions of the layer of silicate glass is between 0.1% to 10%, and wherein the plurality of gates are separated from the common source by the reflown layer of silicate glass.   
     
     
         2 . The semiconductor device of  claim 1 , wherein each gate of the plurality of gates has a V-shaped groove formed within, the V-shaped groove having a first sidewall and a second sidewall, wherein the first sidewall intersects with the second sidewall at an acute angle inside a trench of the plurality of trenches. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the acute angle is less than 60°. 
     
     
         4 . The semiconductor device of  claim 1 , wherein a thickness of the reflown layer of silicate glass directly over the central region is higher than a thickness of the reflown layer of silicate glass directly over a gate dielectric layer. 
     
     
         5 . The semiconductor device of  claim 1 , wherein each of the plurality of trenches is lined with a gate dielectric layer, an insulating layer disposed in a lower portion of a trench of the plurality of trenches, and a gate material above the insulating layer. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising a plurality of contact pads on an upper surface thereof. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the plurality of contact pads are coupled to the plurality of source regions. 
     
     
         8 . A method of forming a transistor comprising:
 forming a plurality of trench gates in a common drain region;   forming a plurality of source regions coupled to a plurality of contact pads;   forming a channel region separating the plurality of source regions from the common drain region;   depositing a conformal BPSG film over the plurality of trench gates and the plurality of source regions; and   terminating the deposition of the conformal BPSG film such that a variation in thickness of the conformal BPSG film is less than 10%.   
     
     
         9 . The method of  claim 8 , further comprising forming a V-shaped groove formed within each trench gate of the plurality of trench gates. 
     
     
         10 . The method of  claim 9 , wherein an angle of the V-shaped groove is less than 60°. 
     
     
         11 . The method of  claim 8 , further comprising forming a plurality of V-shaped grooves in a surface of the transistor. 
     
     
         12 . The method of claim ii, wherein the conformal BPSG film comprises a plurality of V-shaped grooves. 
     
     
         13 . The method of  claim 8 , wherein the plurality of trench gates are electrically isolated from the common drain, the channel region, and the plurality of source regions. 
     
     
         14 . A semiconductor device comprising:
 a plurality of trenches disposed in a semiconductor substrate;   a plurality of gates formed within the plurality of trenches;   a common drain region disposed in the semiconductor substrate;   a plurality of source regions disposed in the semiconductor substrate;   a common source disposed over and coupled to the plurality of source regions; and   a layer of silicate glass disposed over the plurality of gates, wherein a variation in thickness of the layer of silicate glass at a central region of the plurality of gates and other regions of the layer of silicate glass is between 5% to 10%, and wherein the plurality of gates are separated from the common source by the layer of silicate glass.   
     
     
         15 . The semiconductor device of  claim 14 , wherein each gate of the plurality of gates has a V-shaped groove formed within, the V-shaped groove having a first sidewall and a second sidewall, wherein the first sidewall intersects with the second sidewall at an acute angle inside a trench of the plurality of trenches. 
     
     
         16 . The semiconductor device of  claim 15 , wherein the acute angle is less than 60°. 
     
     
         17 . The semiconductor device of  claim 14 , wherein a thickness of the layer of silicate glass directly over the central region is higher than a thickness of the layer of silicate glass directly over a gate dielectric layer. 
     
     
         18 . The semiconductor device of  claim 14 , wherein each of the plurality of trenches is lined with a gate dielectric layer, an insulating layer disposed in a lower portion of a trench of the plurality of trenches, and a gate material above the insulating layer. 
     
     
         19 . The semiconductor device of  claim 14 , further comprising a plurality of contact pads on an upper surface thereof. 
     
     
         20 . The semiconductor device of  claim 19 , wherein the plurality of contact pads are coupled to the plurality of source regions.