Gate stack processes and structures

Abstract

Structures for a field-effect transistor and methods for forming a structure for a field-effect transistor. A gate cavity is formed in a dielectric layer that includes a bottom surface and a plurality sidewalls that extend to the bottom surface. A gate dielectric layer is formed at the sidewalls and the bottom surface of the gate cavity. A work function metal layer is deposited on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity. A fill metal layer is deposited inside the gate cavity after the work function metal layer is deposited. The fill metal layer is formed in direct contact with the work function metal layer.

1 . A method for forming a field-effect transistor, the method comprising:
 forming a gate cavity in a dielectric layer that includes a bottom surface and a plurality of sidewalls extending to the bottom surface;   forming a gate dielectric layer at the sidewalls and the bottom surface of the gate cavity;   depositing a first work function metal layer on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity; and   after the first work function metal layer is deposited, forming a fill metal layer inside the gate cavity,   wherein the fill metal layer is formed in direct contact with the first work function metal layer.   
     
     
         2 . The method of  claim 1  wherein forming the fill metal layer inside the gate cavity that is in direct contact with the first work function metal layer comprises:
 conformally depositing a first fluorine-free tungsten layer on the first work function metal layer. 
 
     
     
         3 . The method of  claim 2  wherein forming the fill metal layer inside the gate cavity that is in direct contact with the first work function metal layer further comprises:
 depositing a conductor layer on the first fluorine-free tungsten layer, 
 wherein the conductor layer fills empty space remaining inside the gate cavity after the first fluorine-free tungsten layer is deposited. 
 
     
     
         4 . The method of  claim 3  wherein the first fluorine-free tungsten layer is formed using atomic layer deposition and a first precursor source that is free of fluorine, and the conductor layer is formed using chemical vapor deposition and a second precursor source that includes fluorine. 
     
     
         5 . The method of  claim 2  further comprising:
 chamfering the first fluorine-free tungsten layer and the first work function metal layer; and 
 conformally depositing a second fluorine-free tungsten layer on the first work function metal layer and the first fluorine-free tungsten layer. 
 
     
     
         6 . The method of  claim 2  wherein the first fluorine-free tungsten layer is formed using atomic layer deposition and a precursor source that is free of fluorine. 
     
     
         7 . The method of  claim 2  wherein the first fluorine-free tungsten layer and the first work function metal layer are deposited in the same deposition tool without an air break. 
     
     
         8 . The method of  claim 1  wherein the bottom surface of the gate cavity opens to a semiconductor fin. 
     
     
         9 . The method of  claim 1  further comprising:
 before forming the first work function metal layer, forming a second work function metal layer on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity after forming the gate dielectric layer; and 
 before forming the first work function metal layer, chamfering the second work function metal layer. 
 
     
     
         10 . The method of  claim 1  further comprising:
 concurrently recessing the fill metal layer and the first work function metal layer; and 
 forming a dielectric cap inside the gate cavity after concurrently recessing the fill metal layer and the first work function metal layer. 
 
     
     
         11 . The method of  claim 10  wherein the first work function metal layer and the fill metal layer are in direct contact with the dielectric cap. 
     
     
         12 . A structure for a field-effect transistor, the method comprising:
 a dielectric layer including a gate cavity with a bottom surface and a plurality of sidewalls that extend to the bottom surface;   a gate dielectric layer at the sidewalls and the bottom surface of the gate cavity;   a first work function metal layer on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity; and   a fill metal layer inside the gate cavity, the fill metal layer in a directly contacting relationship with the first work function metal layer.   
     
     
         13 . The structure of  claim 12  wherein the fill metal layer includes a first fluorine-free tungsten layer arranged on the first work function metal layer. 
     
     
         14 . The structure of  claim 13  wherein the fill metal layer further includes a conductor layer on the first fluorine-free tungsten layer, the conductor layer arranged to fill empty space inside the gate cavity interior of the first fluorine-free tungsten layer. 
     
     
         15 . The structure of  claim 13  further comprising:
 a second fluorine-free tungsten layer on the first work function metal layer and the first fluorine-free tungsten layer. 
 
     
     
         16 . The structure of  claim 15  wherein the first fluorine-free tungsten layer is arranged between the second fluorine-free tungsten layer and the first work function metal layer. 
     
     
         17 . The structure of  claim 13  wherein the first work function metal layer is composed of titanium aluminum carbide. 
     
     
         18 . The structure of  claim 12  further comprising:
 a semiconductor fin, 
 wherein the bottom surface of the gate cavity opens to the semiconductor fin. 
 
     
     
         19 . The structure of  claim 12  further comprising:
 a second work function metal layer at the sidewalls and the bottom surface of the gate cavity, the second work function metal layer arranged between the gate dielectric layer and the first work function metal layer; and 
 a barrier metal layer arranged between the first work function metal layer and the second work function metal layer. 
 
     
     
         20 . The structure of  claim 12  further comprising:
 a dielectric cap inside the gate cavity above the fill metal layer, 
 wherein the first work function metal layer and the fill metal layer have a directly contacting relationship with the dielectric cap.