Semiconductor package

Abstract

A semiconductor package including a first substrate including first upper pads, the first upper pads on a top surface of the first substrate, a second substrate including second upper pads, the second upper pads on a top surface of the second substrate, a pitch of the second upper pads being less than a pitch of the first upper pads, and a first semiconductor chip on and electrically connected to both (i) at least one of the first upper pads and (ii) at least one of the second upper pads may be provided.

What is claimed is: 
     
         1 . A semiconductor package comprising:
 a first substrate including a first top surface and a first bottom surface, the first substrate including first upper pads on the first top surface and a first conductive structure therein;   a second substrate including a second top surface and a second bottom surface, the second substrate including second upper pads on the second top surface and an interconnection, the second upper pads comprising a first sub pad and a second sub pad electrically connected to each other by the interconnection;   a first semiconductor chip on the first substrate and the second substrate, the first semiconductor chip electrically connected to both at least one of the first upper pads and at least one of the second upper pads;   a polymer layer on the first bottom surface of the first substrate and the second bottom surface of the second substrate; and   a bump on the second bottom surface of the second substrate,   wherein a first pitch of the first upper pads is greater than a second pitch of the second upper pads, and   the second top surface of the second substrate is at substantially a same level as the first top surface of the first substrate.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the bump is electrically isolated from the first conductive structure of the first substrate. 
     
     
         3 . The semiconductor package of  claim 1 , wherein
 the second upper pads further comprise a third sub pad,   the second substrate further comprises a second conductive structure electrically connected to the third sub pad, and   the bump is electrically connected to the first semiconductor chip through the second conductive structure.   
     
     
         4 . The semiconductor package of  claim 3 , wherein the second conductive structure electrically isolated from the interconnection. 
     
     
         5 . The semiconductor package of  claim 3 , wherein
 the first substrate further comprises a lower base layer and an upper base layer on the lower base layer, and   the second conductive structure comprises a conductive via penetrating the lower base layer.   
     
     
         6 . The semiconductor package of  claim 5 , wherein the interconnection comprises:
 a first via penetrating the upper base layer and electrically connected to the first sub pad; and   a second via penetrating the upper base layer and electrically connected to the second sub pad.   
     
     
         7 . The semiconductor package of  claim 1 , wherein the bump is electrically isolated from the first semiconductor chip. 
     
     
         8 . The semiconductor package of  claim 1 , wherein
 the first substrate has a hole, and   wherein the second substrate is in the hole of the first substrate.   
     
     
         9 . The semiconductor package of  claim 1 , further comprising:
 a third substrate at a side of the second substrate, the third substrate including a third top surface, the third substrate including third upper pads on the third top surface; and   a second semiconductor chip on the second substrate and the third substrate,   wherein the second semiconductor chip is electrically connected to both at least another of the second upper pads and at least one of the third upper pads.   
     
     
         10 . The semiconductor package of  claim 1 , wherein
 the first substrate further comprises a first lower pad on the first bottom surface, the first lower pad electrically connected to the at least one of the first upper pads, the first lower pad being not vertically aligned with the at least one of the first upper pads.   
     
     
         11 . A semiconductor package comprising:
 a first substrate including a first base substrate and a first conductive structure in the first base substrate, the first substrate including a first top surface and a first bottom surface;   a second substrate including an interconnection, the second substrate including a second top surface and a second bottom surface;   a semiconductor chip on the first top surface of the first substrate and the second top surface of the second substrate;   first connection parts between the first substrate and the semiconductor chip and electrically connected to the first conductive structure;   second connection parts between the second substrate and the semiconductor;   an insulation pattern covering the first bottom surface of the first substrate and the second bottom surface of the second substrate; and   a bump on the second bottom surface of the second substrate;   wherein the interconnection is electrically connected to at least two of the second connection parts, and   a first pitch of the first connection parts is greater than a second pitch of the second connection parts.   
     
     
         12 . The semiconductor package of  claim 11 , wherein the second top surface of the second substrate is at substantially a same level as the first top surface of the first substrate. 
     
     
         13 . The semiconductor package of  claim 11 , wherein
 the second substrate further comprises a second conductive structure therein and is electrically connected to the semiconductor chip, and   the bump is electrically connected to the second conductive structure.   
     
     
         14 . The semiconductor package of  claim 13 , wherein
 the first substrate further comprises a lower base layer and an upper base layer on the lower base layer,   the second conductive structure comprises a conductive via penetrating the lower base layer, and   the interconnection comprises,
 a first via penetrating the upper base layer and electrically connected to one of the second connection parts, and 
 a second via penetrating the upper base layer and electrically connected to another of the second connection parts. 
   
     
     
         15 . The semiconductor package of  claim 11 , further comprising
 a plurality of semiconductor chips including the semiconductor chip,   wherein one of the semiconductor chips is electrically connected to another of the plurality of the semiconductor chips through the interconnection.   
     
     
         16 . A semiconductor package comprising:
 a plurality of semiconductor chips laterally arranged, each of the semiconductor chips including a chip bottom surface, each of the semiconductor chips comprising first pads and second pads on the chip bottom surface;   a first substrate comprising a first conductive structure therein, the first conductive structure electrically connected to at least one of the semiconductor chips through the first pads, the first substrate including a first top surface and a first bottom surface;   a second substrate including interconnections, the interconnections electrically connecting the semiconductor chips to each other through the second pads, the second substrate including a second top surface and a second bottom surface; and   at least one first bump on the second bottom surface of the second substrate and spaced apart from the first substrate,   wherein the chip bottom surface of each of the semiconductor chips faces the first substrate and the second substrate, and   a first pitch of the first pads being greater than a second pitch of the second pads.   
     
     
         17 . The semiconductor package of  claim 16 , further comprising:
 a plurality of second bumps on the first bottom surface of the first substrate and electrically connected to the first conductive structure; and   a package substrate,   wherein the second bumps and the at least one first bump are connected to the package substrate.   
     
     
         18 . The semiconductor package of  claim 16 , further comprising:
 a polymer layer on the first bottom surface of the first substrate and the second bottom surface of the second substrate.   
     
     
         19 . The semiconductor package of  claim 18 , wherein the polymer layer extends in a gap between the first substrate and the second substrate. 
     
     
         20 . The semiconductor package of  claim 16 , wherein the second top surface of the second substrate is at substantially a same level as the first top surface of the first substrate.