Cap Layer For Bit Line Resistance Reduction

Abstract

Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.

What is claimed is: 
     
         1 . A memory device comprising:
 a substrate having at least one film stack thereon, the film stack comprising,
 a polysilicon layer on the substrate; 
 a bit line metal layer on the polysilicon layer; 
 a cap layer on the bit line metal layer; and 
 a hardmask on the cap layer. 
   
     
     
         2 . The memory device of  claim 1 , further comprising a barrier metal layer between the polysilicon layer and the bit line metal layer. 
     
     
         3 . The memory device of  claim 2 , further comprising a barrier layer between the barrier metal layer and the bit line metal layer. 
     
     
         4 . The memory device of  claim 3 , wherein the metal layer comprises one or more of titanium (Ti), tantalum (Ta), titanium silicide (TiSi) or tantalum silicide (TaSi) and the barrier layer comprises titanium nitride (TiN). 
     
     
         5 . The memory device of  claim 1 , wherein the bit line metal layer comprises one or more of tungsten (W), ruthenium (Ru), iridium (Ir) or molybdenum (Mo), platinum (Pt) or rhodium (Rh). 
     
     
         6 . The memory device of  claim 1 , wherein the cap layer comprises silicon nitride (SiN), silicon carbonitride (SiCN), or silicon carbide (SiC). 
     
     
         7 . The memory device of  claim 6 , wherein the cap layer has a thickness in a range of about 30 Å to about 50 Å. 
     
     
         8 . The memory device of  claim 7 , wherein the bit line metal layer has a thickness in a range of about 100 Å to about 300 Å. 
     
     
         9 . The memory device of  claim 1 , wherein the hardmask comprises silicon nitride (SiN). 
     
     
         10 . The memory device of  claim 9 , wherein the cap layer comprises silicon nitride having a different density and/or porosity and/or deposition temperature than the hardmask. 
     
     
         11 . The memory device of  claim 2 , wherein the barrier metal layer comprises one or more of cobalt (Co), copper (Cu), nickel (Ni), ruthenium (Ru), manganese (Mn), silver (Ag), gold (Au), platinum (Pt), iron (Fe), molybdenum (Mo), rhodium (Rh), titanium (Ti), tantalum (Ta), silicon (Si), or tungsten (W). 
     
     
         12 . The memory device of  claim 1 , further comprising a carbon hardmask on the hardmask, an anti-reflective coating (ARC) on the carbon hardmask and a patterned spacer layer on the ARC, wherein the ARC, the carbon hardmask and the hardmask are etched to expose a patterned cap layer by transferring the pattern of the patterned spacer layer into the ARC, reducing a thickness of the patterned spacer layer and forming a patterned ARC, transferring the pattern of the patterned ARC into the carbon hardmask, removing the patterned spacer layer and forming a patterned carbon hardmask, transferring the pattern of the patterned carbon hardmask into the cap layer, removing the patterned ARC and forming a patterned cap layer, and trimming and removing the carbon hardmask from the patterned cap layer. 
     
     
         13 . The memory device of  claim 12 , wherein the patterned cap layer, bit line metal layer, barrier layer, barrier metal layer and polysilicon layer are etched to form a substrate with a plurality of dynamic random access memory (DRAM) film stacks. 
     
     
         14 . A method of forming a memory device, the method comprising:
 providing a substrate having a conductive layer with a barrier layer thereon and a bit line metal layer on the barrier layer;   forming a cap layer on the bit line metal layer at a temperature less than or equal to about 500° C.; and   forming a hardmask on the cap layer at a temperature greater than or equal to about 650° C.,   wherein elements of the hardmask are substantially prevented from migrating into the bit line metal layer.   
     
     
         15 . The method of  claim 14 , wherein the cap layer comprises one or more of silicon nitride or silicon carbonitride. 
     
     
         16 . The method of  claim 15 , wherein the cap layer has a thickness in a range of about 30 Å to about 50 Å. 
     
     
         17 . The method of  claim 16 , wherein the cap layer is deposited by a chemical vapor deposition or atomic layer deposition process. 
     
     
         18 . The method of  claim 17 , wherein the hardmask comprises silicon nitride. 
     
     
         19 . The method of  claim 18 , wherein the hardmask is deposited using a furnace at a temperature greater than or equal to about 650° C.