Semiconductor package and semiconductor manufacturing process

Abstract

A semiconductor package includes a semiconductor substrate structure, a semiconductor die and an encapsulant. The semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post. The first patterned conductive layer is embedded in the dielectric structure. The first insulation layer is disposed on the dielectric structure. The conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer. The first insulation layer has a greater thickness at a position closer to the conductive post. The semiconductor die is electrically connected to the conductive post. The encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a patterned conductive layer; and   an insulation layer covering the pattern conductive layer, wherein the insulation layer defines an opening exposing the first patterned conductive layer, and the first insulation layer comprises a protrusion portion surrounding the opening.   
     
     
         2 . The semiconductor package according to  claim 1 , wherein a top surface of the protrusion portion from a cross-sectional view is a curved surface. 
     
     
         3 . The semiconductor package according to  claim 1 , wherein a thickness of the protrusion portion decreases with increasing distance from the conductive post. 
     
     
         4 . The semiconductor package according to  claim 1 , wherein an inclination angle between a top surface of the protrusion portion and a sidewall of the conductive post is less than 90 degrees. 
     
     
         5 . The semiconductor package according to  claim 1 , further comprising a conductive post disposed in the opening, wherein the conductive post connects to the first patterned conductive layer. 
     
     
         6 . The semiconductor package according to  claim 5 , wherein a surface of the conductive post has a surface roughness (Ra) of greater than about 3 μm. 
     
     
         7 . The semiconductor package according to  claim 5 , wherein the conductive post has a recess which is recessed from a top surface of the conductive post. 
     
     
         8 . The semiconductor package according to  claim 5 , wherein the opening of the insulation layer is spanned by the conductive post. 
     
     
         9 . The semiconductor package according to  claim 1 , further comprising a substrate, wherein the patterned conductive layer is disposed on or embedded in the substrate, and the insulation layer is disposed on the substrate to cover the patterned conductive layer. 
     
     
         10 . The semiconductor package according to  claim 9 , wherein a material of the substrate includes silicon, glass or polymer. 
     
     
         11 . A semiconductor structure, comprising:
 a patterned conductive layer; and   an insulation layer covering the pattern conductive layer, wherein the insulation layer defines an opening exposing the first patterned conductive layer, the insulation layer has a first thickness at a first position and a second thickness at a second position, and the first thickness is greater than the second thickness.   
     
     
         12 . The semiconductor package according to  claim 11 , wherein the first position is closer to the opening than the second position is. 
     
     
         13 . The semiconductor package according to  claim 11 , wherein the first position of the insulation layer has a bottom surface, and the second position of the insulation layer has a bottom surface substantially coplanar with the bottom surface of the first position. 
     
     
         14 . The semiconductor package according to  claim 11 , further comprising a substrate, wherein the patterned conductive layer is disposed on or embedded in the substrate, and the insulation layer is disposed on the substrate to cover the patterned conductive layer. 
     
     
         15 . The semiconductor package according to  claim 14 , wherein a material of the substrate includes silicon, glass or polymer. 
     
     
         16 . The semiconductor package according to  claim 11 , further comprising a semiconductor die, wherein the patterned conductive layer is disposed on or embedded in the semiconductor die, and the insulation layer is disposed on the semiconductor die to cover the patterned conductive layer. 
     
     
         17 . The semiconductor package according to  claim 11 , further comprising a conductive post disposed in the opening, wherein a top surface of the conductive post is lower than a top surface of the insulation layer 
     
     
         18 . The semiconductor package according to  claim 17 , wherein the conductive post and the patterned conductive layer are formed integrally. 
     
     
         19 . The semiconductor package according to  claim 17 , wherein the conductive post has a consistent width. 
     
     
         20 . The semiconductor package according to  claim 17 , wherein the patterned conductive layer includes a bump pad and a trace, and the conductive post and the bump pad of the first patterned conductive layer are formed integrally.