Chip scale package structure and method of forming the same

Abstract

A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.

What is claimed is: 
     
         1 . A semiconductor package structure, comprising:
 a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface;   a redistribution layer (RDL) structure on the first surface of the semiconductor die and electrically coupled to the semiconductor die;   a protective insulating layer covering the RDL structure, the second surface and the third surface of the semiconductor die; and   a conductive structure passing through the protective insulating layer and electrically coupled to the RDL structure.   
     
     
         2 . The semiconductor package structure as claimed in  claim 1 , further comprising a passivation layer between the RDL structure and the protective insulating layer and covered by the protective insulating layer, wherein the conductive structure passes through the passivation layer. 
     
     
         3 . The semiconductor package structure as claimed in  claim 1 , further comprising a passivation layer between the first surface of the semiconductor die and the RDL structure, wherein the RDL structure passes through the passivation layer. 
     
     
         4 . The semiconductor package structure as claimed in  claim 1 , further comprising:
 a first passivation layer between the first surface of the semiconductor die and the RDL structure, wherein the RDL structure passes through the first passivation layer; and   a second passivation layer between the RDL structure and the protective insulating layer and covered by the protective insulating layer, wherein the conductive structure passes through the second passivation layer.   
     
     
         5 . The semiconductor package structure as claimed in  claim 4 , wherein the first passivation layer comprises a material that is the same as a material of the second passivation layer and different from a material of the protective insulating layer. 
     
     
         6 . The semiconductor package structure as claimed in  claim 4 , wherein the first passivation layer and the second passivation layer respectively comprise polyimide or polybenzoxazole (PBO). 
     
     
         7 . The semiconductor package structure as claimed in  claim 1 , wherein the protective insulating layer comprises an epoxy molding compound (EMC), an Ajinomoto™ Build-up Film (ABF), or an acrylic-based material. 
     
     
         8 . The semiconductor package structure as claimed in  claim 1 , wherein the conductive structure comprises an under-bump metallurgy (UBM) layer and a solder bump on the UBM layer, or a solder bump on the first passivation layer. 
     
     
         9 . A semiconductor package structure, comprising:
 a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface;   a first protective insulating layer covering the first surface and the third surface of the semiconductor die;   a first redistribution layer (RDL) structure over the first surface of the semiconductor die and electrically coupled to the semiconductor die and extending to directly above the first protective insulating layer;   a first passivation layer covering the first protective insulating layer and the first RDL structure; and   a plurality of conductive structures passing through the first passivation layer and electrically coupled to the first RDL structure.   
     
     
         10 . The semiconductor package structure as claimed in  claim 9 , further comprising a second RDL structure between the first RDL structure and the first surface of the semiconductor die and electrically coupled to the semiconductor die. 
     
     
         11 . The semiconductor package structure as claimed in  claim 10 , wherein the second RDL structure is surrounded by the first protective insulating layer on the first surface of the semiconductor die. 
     
     
         12 . The semiconductor package structure as claimed in  claim 10 , wherein the first RDL structure is electrically coupled to the semiconductor die through the second RDL structure. 
     
     
         13 . The semiconductor package structure as claimed in  claim 10 , further comprising a second passivation layer between the second RDL structure and the first surface of the semiconductor die, wherein the second RDL structure passes through the second passivation layer. 
     
     
         14 . The semiconductor package structure as claimed in  claim 13 , wherein the second passivation layer is surrounded by the first protective insulating layer on the first surface of the semiconductor die. 
     
     
         15 . The semiconductor package structure as claimed in  claim 13 , wherein the second passivation layer comprises a material that is the same as a material of the first passivation layer and different from a material of the first protective insulating layer. 
     
     
         16 . The semiconductor package structure as claimed in  claim 9 , further comprising a second passivation layer between the first RDL structure and the first protective insulating layer, wherein the first RDL structure passes through the second passivation layer. 
     
     
         17 . The semiconductor package structure as claimed in  claim 16 , wherein the second passivation layer comprises a material that is the same as a material of the first passivation layer and different from a material of the first protective insulating layer. 
     
     
         18 . The semiconductor package structure as claimed in  claim 9 , further comprising a second protective insulating layer covering the second surface of the semiconductor die. 
     
     
         19 . The semiconductor package structure as claimed in  claim 18 , wherein the first protective insulating layer and the second protective insulating layer comprise the same material. 
     
     
         20 . The semiconductor package structure as claimed in  claim 18 , wherein the first protective insulating layer and the second protective insulating layer respectively comprise an epoxy molding compound (EMC), an Ajinomoto™ Build-up Film (ABF), or an acrylic-based material. 
     
     
         21 . The semiconductor package structure as claimed in  claim 9 , wherein the conductive structure comprises an under-bump metallurgy (UBM) layer and a solder bump on the UBM layer, or a solder bump on the first passivation layer. 
     
     
         22 . A semiconductor package structure, comprising:
 a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface;   a first redistribution layer (RDL) structure on the first surface of the semiconductor die and electrically coupled to the semiconductor die;   a first protective insulating layer covering the first surface and the third surface of the semiconductor die and surrounding the first RDL structure;   a first passivation layer covering the first protective insulating layer and the first RDL structure;   a second RDL structure electrically coupled to the semiconductor die through the first RDL structure, wherein the second RDL structure extends from the first RDL structure to above the first protective insulating layer;   a second passivation layer covering the second RDL structure; and   a plurality of conductive structures passing through the second passivation layer and electrically coupled to the second RDL structure.   
     
     
         23 . The semiconductor package structure as claimed in  claim 22 , further comprising a second protective insulating layer covering the second surface of the semiconductor die. 
     
     
         24 . The semiconductor package structure as claimed in  claim 22 , further comprising a third passivation layer between the first surface of the semiconductor die and the first RDL structure, wherein the first RDL structure passes through the third passivation layer. 
     
     
         25 . The semiconductor package structure as claimed in  claim 24 , wherein the third passivation layer is surrounded and covered by the first protective insulating layer. 
     
     
         26 . The semiconductor package structure as claimed in  claim 24 , wherein the first passivation layer, the second passivation layer and the third passivation layer comprise a material that is different from a material of the first protective insulating layer. 
     
     
         27 . The semiconductor package structure as claimed in  claim 24 , wherein the first passivation layer, the second passivation layer and the third passivation layer respectively comprise polyimide or polybenzoxazole (PBO). 
     
     
         28 . The semiconductor package structure as claimed in  claim 22 , wherein the conductive structure comprises an under-bump metallurgy (UBM) layer and a solder bump on the UBM layer, or a solder bump on the second passivation layer.