Conductive metal oxide structures in non-volatile re-writable memory devices

Abstract

A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

1 . (canceled) 
     
     
         2 . An integrated circuit comprising:
 a base layer; and   a plurality of memory layers formed above the base layer, each of the plurality of memory layers comprising a cross-point memory array comprising a plurality of row conductors and a plurality of column conductors arranged substantially orthogonal to the plurality of row conductors, where intersections between the plurality of row conductors and the plurality of column conductors form a plurality of memory cells, each of the plurality of memory cells comprising:
 an electrolytic insulator layer; and 
 a conductive metal oxide layer in contact with the electrolytic insulator layer and configured to be reversibly programmable between multiple resistance states via exchange of mobile ions with the electrolytic insulator layer. 
   
     
     
         3 . The integrated circuit of  claim 2 , wherein the electrolytic insulator layer and the conductive oxide layer are configured to store at least one bit of data as a plurality of conductivity profiles that are retained in an absence of electrical power. 
     
     
         4 . The integrated circuit of  claim 2 , wherein each of the plurality of memory layers are electrically isolated from adjacent layers by a dielectric material. 
     
     
         5 . The integrated circuit of  claim 2 , wherein the base layer comprises a plurality of active memory access circuits. 
     
     
         6 . The integrated circuit of  claim 5 , wherein the base layer comprises a bulk silicon semiconductor substrate upon which the plurality of active memory access circuits are formed, the active memory access circuits to perform data operations on the plurality of memory layers. 
     
     
         7 . The integrated circuit of  claim 5 , further comprising:
 an inter-level interconnect structure configured to electrically couple the plurality of row conductors and the plurality of column conductors to the plurality of active memory access circuits.   
     
     
         8 . The integrated circuit of  claim 7 , wherein the active memory access circuits are configured to apply a select voltage potential to selected row conductors and column conductors of the cross-point memory array through the inter-level interconnect structure. 
     
     
         9 . The integrated circuit of  claim 2 , further comprising:
 an address unit coupled to the cross-point memory array, wherein the address unit is configured to receive an address, decode the address, and select a memory cell corresponding to the address from the cross-point memory array; and   a sense unit coupled to the cross-point memory array, wherein the sense unit is configured to sense one or more currents flowing through the row conductors or column conductors, the one or more currents indicative of stored data in the memory cell.   
     
     
         10 . A memory device comprising:
 a base layer; and   a memory layers formed above the base layer, the memory layer comprising a cross-point memory array comprising a plurality of row conductors and a plurality of column conductors arranged substantially orthogonal to the plurality of row conductors, where intersections between the plurality of row conductors and the plurality of column conductors form a plurality of memory cells, each of the plurality of memory cells comprising:
 an electrolytic insulator layer; and 
 a conductive metal oxide layer in contact with the electrolytic insulator layer and configured to be reversibly programmable between multiple resistance states via exchange of mobile ions with the electrolytic insulator layer. 
   
     
     
         11 . The memory device of  claim 10 , wherein the electrolytic insulator layer and the conductive oxide layer are configured to store at least one bit of data as a plurality of conductivity profiles that are retained in an absence of electrical power. 
     
     
         12 . The memory device of  claim 10 , wherein the base layer comprises a plurality of active memory access circuits. 
     
     
         13 . The memory device of  claim 12 , wherein the base layer comprises a bulk silicon semiconductor substrate upon which the plurality of active memory access circuits are formed, the active memory access circuits to perform data operations on the memory layer. 
     
     
         14 . The memory device of  claim 12 , further comprising:
 an inter-level interconnect structure configured to electrically couple the plurality of row conductors and the plurality of column conductors to the plurality of active memory access circuits.   
     
     
         15 . The memory device of  claim 14 , wherein the active memory access circuits are configured to apply a select voltage potential to selected row conductors and column conductors of the cross-point memory array through the inter-level interconnect structure. 
     
     
         16 . The memory device of  claim 10 , further comprising:
 an address unit coupled to the cross-point memory array, wherein the address unit is configured to receive an address, decode the address, and select a memory cell corresponding to the address from the cross-point memory array; and   a sense unit coupled to the cross-point memory array, wherein the sense unit is configured to sense one or more currents flowing through the row conductors or column conductors, the one or more currents indicative of stored data in the memory cell.   
     
     
         17 . An multi-layer memory circuit comprising:
 a plurality of memory layers, each of the plurality of memory layers comprising a cross-point memory array comprising a plurality of row conductors and a plurality of column conductors arranged substantially orthogonal to the plurality of row conductors, where intersections between the plurality of row conductors and the plurality of column conductors form a plurality of memory cells, each of the plurality of memory cells comprising:
 an electrolytic insulator layer; and 
 a conductive metal oxide layer in contact with the electrolytic insulator layer and configured to be reversibly programmable between multiple resistance states via exchange of mobile ions with the electrolytic insulator layer. 
   
     
     
         18 . The multi-layer memory circuit of  claim 17 , wherein the electrolytic insulator layer and the conductive oxide layer are configured to store at least one bit of data as a plurality of conductivity profiles that are retained in an absence of electrical power. 
     
     
         19 . The multi-layer memory circuit of  claim 17 , wherein each of the plurality of memory layers are electrically isolated from adjacent layers by a dielectric material. 
     
     
         20 . The multi-layer memory circuit of  claim 17 , wherein memory cells in adjacent layers of the plurality of memory layers share at least one of the plurality of row conductors or the plurality of column conductors. 
     
     
         21 . The multi-layer memory circuit of  claim 17 , further comprising:
 an address unit coupled to the cross-point memory array, wherein the address unit is configured to receive an address, decode the address, and select a memory cell corresponding to the address from the cross-point memory array; and   a sense unit coupled to the cross-point memory array, wherein the sense unit is configured to sense one or more currents flowing through the row conductors or column conductors, the one or more currents indicative of stored data in the memory cell.