Recessed STI as the Gate Dielectric of HV Device

Abstract

A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.

What is claimed is: 
     
         1 . A device comprising:
 a semiconductor substrate;   an isolation region extending into the semiconductor substrate, wherein the isolation region comprises:
 a first bottom portion having a first top surface; 
 first sidewall portions higher than the first top surface, wherein the first sidewall portions are connected to opposing ends of the first bottom portion; 
   a gate dielectric having an U-shape in a cross-sectional view of the device, the gate dielectric comprising:
 a second bottom portion over and contacting the first top surface; and 
 second sidewall portions over and connecting to opposing ends of the second bottom portion; 
   a first well region; and   a second well region, wherein the first well region and the second well region extend to opposite sides of the isolation region, and wherein both of the first well region and the second well region contact the first bottom portion and the first sidewall portions of the isolation region.   
     
     
         2 . The device of  claim 1 , wherein the second bottom portion is substantially planar. 
     
     
         3 . The device of  claim 1  further comprising a gate spacer contacting the gate dielectric, wherein the gate spacer extends lower than a top surface of one of the first sidewall portions. 
     
     
         4 . The device of  claim 3 , wherein the gate spacer is between, and is spaced apart from, the first sidewall portions of the isolation region. 
     
     
         5 . The device of  claim 1  further comprising a contact etch stop layer (CESL), wherein the CESL extends into a space between the gate dielectric and one of the first sidewall portions, and extends lower than a top surface of the one of the first sidewall portions. 
     
     
         6 . The device of  claim 5  further comprising an inter-layer dielectric over the CESL, wherein the inter-layer dielectric extends into the space, and extends lower than the top surface of the one of the first sidewall portions. 
     
     
         7 . The device of  claim 1  further comprising:
 a first High Voltage Well (HVW) region of a first conductivity type, wherein the first HVW region comprises a portion directly underlying the gate dielectric; and 
 a second HVW region and a third HVW region on opposing sides of, and joining to, the first HVW region, wherein the second HVW region and a third HVW region contact sidewalls of the first sidewall portions of the isolation region. 
 
     
     
         8 . The device of  claim 7 , wherein first HVW region extends laterally beyond, and is wider than, the gate dielectric. 
     
     
         9 . The device of  claim 1 , wherein an entirety of the second bottom portion of the gate dielectric is lower than top ends of the first sidewall portions of the isolation region. 
     
     
         10 . The device of  claim 1  further comprising a transistor, wherein the transistor comprises an additional gate dielectric higher than top edges of the first sidewall portions of the isolation region. 
     
     
         11 . A device comprising:
 a semiconductor substrate;   an isolation region comprising edge portions and a middle portion between the edge portions, wherein the middle portion is recessed lower than the edge portions to form a recess;   a gate stack extending into the recess;   a gate spacer on a sidewall of the gate stack, wherein the gate spacer extends into the recess; and   a first source/drain region and a second source/drain region extending into the semiconductor substrate, wherein the first source/drain region and the second source/drain region are on opposite sides of the isolation region.   
     
     
         12 . The device of  claim 11 , wherein a top surface of the middle portion of the isolation region is lower than a top surface of the semiconductor substrate. 
     
     
         13 . The device of  claim 11 , wherein the gate stack comprises a gate dielectric having a U-shape in a cross-sectional view of the device, wherein the U-shape comprises a bottom part, and two sidewall parts connecting to opposite ends of the bottom part, and wherein an entirety of the bottom part is in the recess. 
     
     
         14 . The device of  claim 11 , wherein the gate spacer is between, and is laterally spaced apart from both of, the edges portions of the isolation region. 
     
     
         15 . The device of  claim 11  further comprising a contact etch stop layer, wherein the contact etch stop layer comprises a portion inside the recess. 
     
     
         16 . The device of  claim 15  further comprising an inter-layer dielectric over the contact etch stop layer, wherein the inter-layer dielectric further extends into the recess. 
     
     
         17 . A device comprising:
 a semiconductor substrate;   a first well region of a first conductivity type in the semiconductor substrate;   a second well region and a third well region on opposing sides of the first well region and in the semiconductor substrate, wherein the second well region and the third well region are of a second conductivity type opposite to the first conductivity type;   an isolation region extending into the first well region, the second well region, and the third well region; and   a transistor comprising:
 a gate stack; 
 gate spacers on opposing sides of the gate stack, wherein both of the gate stack and the gate spacers extend into the isolation region; 
 a first source/drain region in the second well region; and 
 a second source/drain region in the third well region, wherein the first source/drain region and the second source/drain region are on opposite sides of, and are spaced apart from, the isolation region. 
   
     
     
         18 . The device of  claim 17 , wherein the isolation region comprises:
 a bottom part; and   a first sidewall part and a second sidewall part over and connected to the bottom part, wherein the gate spacers are between, and are separated from, the first sidewall part and the second sidewall part.   
     
     
         19 . The device of  claim 17  further comprising an additional isolation region in the semiconductor substrate, wherein the additional isolation region has a substantially planar top surface, and a sidewall of the additional isolation region contacts the first source/drain region. 
     
     
         20 . The device of  claim 17  further comprising a dielectric layer extending into the isolation region, wherein the dielectric layer contacts the gate spacers.