Method of fabricating a semiconductor device having reduced contact resistance

Abstract

Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.

What is claimed is: 
     
         1 . A processing system comprising:
 a first transfer chamber;   a plurality of process chambers coupled to the first transfer chamber; and   a controller operatively coupled to the plurality of process chambers, the controller configured to cause a process to be performed in the processing system that includes:
 performing a pre-clean process on a source/drain region; 
 forming a doped semiconductor layer on the source/drain region; and 
 filling a trench with a conductor. 
   
     
     
         2 . The processing system of  claim 1 , wherein the plurality of process chambers comprises a first process chamber configured to perform an epitaxial deposition process. 
     
     
         3 . The processing system of  claim 2 , wherein the plurality of process chambers further comprises a second process chamber configured to perform the pre-clean process. 
     
     
         4 . The processing system of  claim 3 , further comprising a second transfer chamber coupled to the first transfer chamber by pass-through chambers. 
     
     
         5 . The processing system of  claim 1 , wherein the controller is further configured to cause the process to include:
 forming a metal silicide layer on the doped semiconductor layer;   forming a cap layer on the metal silicide layer;   disposing the conductor on the cap layer; and   disposing a contact etch stop layer on a portion of the source/drain region.   
     
     
         6 . The processing system of  claim 5 , wherein the doped semiconductor layer comprises doped silicon, doped germanium, doped silicon-germanium, or doped group III/V compound semiconductors, and the doped semiconductor layer is formed by a selective epitaxial deposition process. 
     
     
         7 . The processing system of  claim 6 , wherein the metal silicide layer comprises titanium silicide, cobalt silicide, or ruthenium silicide, and the metal silicide layer is formed by the selective epitaxial deposition process. 
     
     
         8 . The processing system of  claim 7 , wherein the cap layer comprises titanium nitride, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or manganese oxide, and the cap layer is formed by an atomic layer deposition process. 
     
     
         9 . The processing system of  claim 8 , wherein the conductor comprises a metal. 
     
     
         10 . The processing system of  claim 1 , wherein the controller is further configured to cause the process to be performed in the processing system to form a semiconductor device comprising:
 the source/drain region extending between a dielectric material and a semiconductor structure;   the doped semiconductor layer disposed on a first portion of the source/drain region;   a metal silicide layer disposed on the doped semiconductor layer;   the conductor filled in a trench, wherein the trench is formed in the dielectric material to expose the source/drain region;   a cap layer disposed on the metal silicide layer and the dielectric material;   a conductor disposed on the cap layer; and   a contact etch stop layer disposed on a second portion of the source/drain region.   
     
     
         11 . The processing system of  claim 10 , wherein the source/drain region comprises silicon, germanium, silicon-germanium, or group III/V compound semiconductors. 
     
     
         12 . The processing system of  claim 11 , wherein the semiconductor structure comprises silicon, germanium, silicon-germanium, or group III/V compound semiconductors. 
     
     
         13 . The processing system of  claim 12 , wherein the doped semiconductor layer comprises doped silicon, doped germanium, doped silicon-germanium, or doped group III/V compound semiconductors, and the doped semiconductor layer is formed by a selective epitaxial deposition process. 
     
     
         14 . The processing system of  claim 13 , wherein the metal silicide layer comprises titanium silicide, cobalt silicide, or ruthenium silicide. 
     
     
         15 . The processing system of  claim 14 , wherein the cap layer comprises titanium nitride, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or manganese oxide. 
     
     
         16 . The processing system of  claim 15 , wherein the conductor comprises a metal. 
     
     
         17 . The processing system of  claim 10 , wherein the contact etch stop layer comprises silicon nitride, silicon oxynitride, silicon carbon nitride, or a combination thereof.